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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / EnablePort5_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 13:41:44
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(*
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Original block name: EnablePort5_PP/Enabled_Counter/Subsystem
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*)
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node  Subsystem_30_930_condExecSS(In1_1 : real;
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	Enable_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;);
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var pre_Out1_1 : real;
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	pre_Out2_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1) = (merge _isEnabled_clock 
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		(true -> Subsystem_30_930((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: EnablePort5_PP/Enabled_Counter/Subsystem
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*)
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node  Subsystem_30_930(In1_1 : real;
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	Enable_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + In1_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = Add_1;
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	Out2_1 = Enable_1;
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tel
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(*
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Original block name: EnablePort5_PP/Enabled_Counter
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*)
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node  Enabled_Counter_18_598_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var pre_Out1_1 : real;
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	pre_Out2_1 : real;
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	pre_Out3_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	pre_Out3_1 = if (__nb_step > 0) then
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		(pre Out3_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1, Out3_1) = (merge _isEnabled_clock 
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		(true -> Enabled_Counter_18_598((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: EnablePort5_PP/Enabled_Counter
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*)
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node  Enabled_Counter_18_598(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var Add_1 : real;
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	ExecutionCond_of_Subsystem_30_930 : bool;
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	Subsystem_1 : real;
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	Subsystem_2 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + In1_1 + UnitDelay_1;
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	ExecutionCond_of_Subsystem_30_930 = (In1_1 > 0.0);
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	(Subsystem_1, Subsystem_2) = Subsystem_30_930_condExecSS(In1_1, In1_1, ExecutionCond_of_Subsystem_30_930, __time_step, __nb_step);
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = Add_1;
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	Out2_1 = Subsystem_1;
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	Out3_1 = Subsystem_2;
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tel
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(*
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Original block name: EnablePort5_PP
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*)
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node  EnablePort5_PP(In1_1 : real;
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	Enable_1 : real;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var ExecutionCond_of_Enabled_Counter_18_598 : bool;
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	Enabled_Counter_1 : real;
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	Enabled_Counter_2 : real;
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	Enabled_Counter_3 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	ExecutionCond_of_Enabled_Counter_18_598 = (Enable_1 > 0.0);
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	(Enabled_Counter_1, Enabled_Counter_2, Enabled_Counter_3) = Enabled_Counter_18_598_condExecSS(In1_1, ExecutionCond_of_Enabled_Counter_18_598, __time_step, __nb_step);
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	Out1_1 = Enabled_Counter_1;
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	Out2_1 = Enabled_Counter_2;
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	Out3_1 = Enabled_Counter_3;
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	__time_step = (0.0 -> ((pre __time_step) + 0.20));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel
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