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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / EnablePort4_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 13:41:12
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(*
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Original block name: EnablePort4_PP/case_held_held_held
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*)
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node  case_held_held_held_18_597_condExecSS(Cpre_compx_1 : real;
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	Enable_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var pre_Ccor_x_1 : real;
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	pre_pre_x_1 : real;
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	pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Ccor_x_1 = if (__nb_step > 0) then
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		(pre Ccor_x_1)
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	    else 0.0;
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	pre_pre_x_1 = if (__nb_step > 0) then
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		(pre pre_x_1)
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	    else 0.0;
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
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		(true -> case_held_held_held_18_597((Cpre_compx_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: EnablePort4_PP/case_held_held_held
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*)
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node  case_held_held_held_18_597(Cpre_compx_1 : real;
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	Enable_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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	UnitDelay1_1 : real;
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let
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	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	UnitDelay1_1 = (0.0 -> (pre Cpre_compx_1));
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	Ccor_x_1 = Add_1;
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	pre_x_1 = UnitDelay1_1;
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	Out1_1 = Enable_1;
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tel
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(*
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Original block name: EnablePort4_PP
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*)
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node  EnablePort4_PP(In1_1 : real;
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	In2_1 : real;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var ExecutionCond_of_case_held_held_held_18_597 : bool;
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	case_held_held_held_1 : real;
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	case_held_held_held_2 : real;
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	case_held_held_held_3 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	ExecutionCond_of_case_held_held_held_18_597 = (In1_1 > 0.0);
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	(case_held_held_held_1, case_held_held_held_2, case_held_held_held_3) = case_held_held_held_18_597_condExecSS(In2_1, In1_1, ExecutionCond_of_case_held_held_held_18_597, __time_step, __nb_step);
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	Out1_1 = case_held_held_held_1;
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	Out2_1 = case_held_held_held_2;
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	Out3_1 = case_held_held_held_3;
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	__time_step = (0.0 -> ((pre __time_step) + 0.20));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel
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