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Revision b58cc410 regression_tests/lustre_files/success/Simulink/src_many_files/enable_test3_PP.LUSTREC.lus

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regression_tests/lustre_files/success/Simulink/src_many_files/enable_test3_PP.LUSTREC.lus
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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (ToLustre.m)
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-- Time: 03-Dec-2018 22:35:29
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 13:44:56
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node  bool_to_real(x : bool;)
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returns(y : real;);
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let
......
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(*
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Original block name: enable_test3_PP/Subsystem1
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*)
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node  Subsystem1_66_067_automaton(In1_1 : real;
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node  Subsystem1_18_600_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.000000000000000;
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	automaton enabled_Subsystem1_66_067
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	state Active_Subsystem1_66_067:
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	unless (not _isEnabled) restart Inactive_Subsystem1_66_067
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	let
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		Out1_1 = Subsystem1_66_067(In1_1, Enable_1, __time_step, __nb_step);
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	tel
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	state Inactive_Subsystem1_66_067:
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	unless _isEnabled restart Active_Subsystem1_66_067
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	let
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		Out1_1 = pre_Out1_1;
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	tel
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> (Subsystem1_18_600((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test3_PP/Subsystem1
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*)
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node  Subsystem1_66_067(In1_1 : real;
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node  Subsystem1_18_600(In1_1 : real;
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	Enable_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
......
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + bool_to_real(Enable_1) + In1_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = UnitDelay_1;
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tel
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(*
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Original block name: enable_test3_PP/Subsystem2
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*)
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node  Subsystem2_77_065_automaton(In1_1 : real;
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node  Subsystem2_47_603_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.000000000000000;
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	automaton enabled_Subsystem2_77_065
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	state Active_Subsystem2_77_065:
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	unless (not _isEnabled) restart Inactive_Subsystem2_77_065
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	let
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		Out1_1 = Subsystem2_77_065(In1_1, Enable_1, __time_step, __nb_step);
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	tel
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	state Inactive_Subsystem2_77_065:
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	unless _isEnabled restart Active_Subsystem2_77_065
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	let
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		Out1_1 = pre_Out1_1;
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	tel
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> (Subsystem2_47_603((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test3_PP/Subsystem2
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*)
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node  Subsystem2_77_065(In1_1 : real;
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node  Subsystem2_47_603(In1_1 : real;
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	Enable_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
......
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	Memory_1 : real;
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let
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	Add_1 = 0.0 + bool_to_real(Enable_1) + In1_1;
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	Memory_1 = (0.000000000000000 -> (pre Add_1));
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	Memory_1 = (0.0 -> (pre Add_1));
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	Out1_1 = Memory_1;
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tel
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(*
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Original block name: enable_test3_PP/Subsystem3
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*)
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node  Subsystem3_87_284_automaton(In1_1 : real;
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node  Subsystem3_69_360_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.000000000000000;
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	automaton enabled_Subsystem3_87_284
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	state Active_Subsystem3_87_284:
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	unless (not _isEnabled) restart Inactive_Subsystem3_87_284
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	let
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		Out1_1 = Subsystem3_87_284(In1_1, Enable_1, __time_step, __nb_step);
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	tel
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	state Inactive_Subsystem3_87_284:
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	unless _isEnabled resume Active_Subsystem3_87_284
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	let
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		Out1_1 = pre_Out1_1;
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	tel
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> Subsystem3_69_360((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test3_PP/Subsystem3
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*)
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node  Subsystem3_87_284(In1_1 : real;
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node  Subsystem3_69_360(In1_1 : real;
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	Enable_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
......
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var ExecutionCond_of_Subsystem1_66_067 : bool;
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var ExecutionCond_of_Subsystem1_18_600 : bool;
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	Subsystem1_1 : real;
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	ExecutionCond_of_Subsystem2_77_065 : bool;
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	ExecutionCond_of_Subsystem2_47_603 : bool;
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	Subsystem2_1 : real;
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	ExecutionCond_of_Subsystem3_87_284 : bool;
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	ExecutionCond_of_Subsystem3_69_360 : bool;
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	Subsystem3_1 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	ExecutionCond_of_Subsystem1_66_067 = In2_1;
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	Subsystem1_1 = Subsystem1_66_067_automaton(In1_1, In2_1, ExecutionCond_of_Subsystem1_66_067, __time_step, __nb_step);
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	ExecutionCond_of_Subsystem2_77_065 = In2_1;
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	Subsystem2_1 = Subsystem2_77_065_automaton(In1_1, In2_1, ExecutionCond_of_Subsystem2_77_065, __time_step, __nb_step);
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	ExecutionCond_of_Subsystem3_87_284 = In2_1;
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	Subsystem3_1 = Subsystem3_87_284_automaton(In1_1, In2_1, ExecutionCond_of_Subsystem3_87_284, __time_step, __nb_step);
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	ExecutionCond_of_Subsystem1_18_600 = In2_1;
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	Subsystem1_1 = Subsystem1_18_600_condExecSS(In1_1, In2_1, ExecutionCond_of_Subsystem1_18_600, __time_step, __nb_step);
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	ExecutionCond_of_Subsystem2_47_603 = In2_1;
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	Subsystem2_1 = Subsystem2_47_603_condExecSS(In1_1, In2_1, ExecutionCond_of_Subsystem2_47_603, __time_step, __nb_step);
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	ExecutionCond_of_Subsystem3_69_360 = In2_1;
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	Subsystem3_1 = Subsystem3_69_360_condExecSS(In1_1, In2_1, ExecutionCond_of_Subsystem3_69_360, __time_step, __nb_step);
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	Out1_1 = Subsystem1_1;
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	Out2_1 = Subsystem2_1;
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	Out3_1 = Subsystem3_1;
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	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
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	__time_step = (0.0 -> ((pre __time_step) + 0.20));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel
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