Project

General

Profile

Revision b58cc410 regression_tests/lustre_files/success/Simulink/src_many_files/enable_test2_PP.LUSTREC.lus

View differences:

regression_tests/lustre_files/success/Simulink/src_many_files/enable_test2_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:35:16
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:44:19
5
node  Subsystem0_19_615_triggeredSS(In1_1 : real;
6
	_isEnabled : bool;
7
	_isTriggered : bool;
8
	__time_step : real;
9
	__nb_step : int;)
10
returns(Out1_1 : real;);
11
var pre_Out1_1 : real;
12
	_isTriggered_clock : bool clock;
13
let
14
	pre_Out1_1 = if (__nb_step > 0) then
15
		(pre Out1_1)
16
	    else 0.0;
17
	_isTriggered_clock = _isTriggered;
18
	Out1_1 = (merge _isTriggered_clock 
19
		(true -> Subsystem0_19_615((In1_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
20
		(false -> (pre_Out1_1) when false(_isTriggered_clock)));
21
tel
22

  
5 23
(*
6 24
Original block name: enable_test2_PP/Subsystem0
7 25
*)
8
node  Subsystem0_90_482_automaton(In1_1 : real;
26
node  Subsystem0_19_615_condExecSS(In1_1 : real;
9 27
	_isEnabled : bool;
10 28
	_isTriggered : bool;
11 29
	__time_step : real;
12 30
	__nb_step : int;)
13 31
returns(Out1_1 : real;);
14 32
var pre_Out1_1 : real;
33
	_isEnabled_clock : bool clock;
15 34
let
16 35
	pre_Out1_1 = if (__nb_step > 0) then
17 36
		(pre Out1_1)
18
	    else 0.000000000000000;
19
	automaton enabled_Subsystem0_90_482
20
	state Active_Subsystem0_90_482:
21
	unless (not _isEnabled) restart Inactive_Subsystem0_90_482
22
	let
23
		automaton triggered_Subsystem0_90_482
24
	state Active_triggered_Subsystem0_90_482:
25
	unless (not _isTriggered) resume Inactive_triggered_Subsystem0_90_482
26
	let
27
		Out1_1 = Subsystem0_90_482(In1_1, __time_step, __nb_step);
28
	tel
29

  
30
	state Inactive_triggered_Subsystem0_90_482:
31
	unless _isTriggered resume Active_triggered_Subsystem0_90_482
32
	let
33
		Out1_1 = pre_Out1_1;
34
	tel
35

  
36

  
37
	tel
38

  
39
	state Inactive_Subsystem0_90_482:
40
	unless _isEnabled resume Active_Subsystem0_90_482
41
	let
42
		Out1_1 = pre_Out1_1;
43
	tel
44

  
45

  
37
	    else 0.0;
38
	_isEnabled_clock = _isEnabled;
39
	Out1_1 = (merge _isEnabled_clock 
40
		(true -> Subsystem0_19_615_triggeredSS((In1_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
41
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
46 42
tel
47 43

  
48 44
(*
49 45
Original block name: enable_test2_PP/Subsystem0
50 46
*)
51
node  Subsystem0_90_482(In1_1 : real;
47
node  Subsystem0_19_615(In1_1 : real;
52 48
	__time_step : real;
53 49
	__nb_step : int;)
54 50
returns(Out1_1 : real;);
......
57 53
tel
58 54

  
59 55
(*
60
Original block name: enable_test2_PP/Subsystem1/CompareToZero
56
Original block name: enable_test2_PP/Subsystem1/Compare
57
To Zero
61 58
*)
62
node  CompareToZero_101_043(u_1 : real;
59
node  CompareToZero_54_666(u_1 : real;
63 60
	__time_step : real;
64 61
	__nb_step : int;)
65 62
returns(y_1 : bool;);
......
67 64
	Constant_1 : real;
68 65
let
69 66
	Compare_1 = (u_1 <= Constant_1);
70
	Constant_1 = 0.000000000000000;
67
	Constant_1 = 0.0;
71 68
	y_1 = Compare_1;
72 69
tel
73 70

  
71
node  Subsystem1_40_723_triggeredSS(In1_1 : real;
72
	Enable_1 : bool;
73
	Trigger_1 : real;
74
	_isEnabled : bool;
75
	_isTriggered : bool;
76
	__time_step : real;
77
	__nb_step : int;)
78
returns(Out1_1 : bool;
79
	Out2_1 : real;);
80
var pre_Out1_1 : bool;
81
	pre_Out2_1 : real;
82
	_isTriggered_clock : bool clock;
83
let
84
	pre_Out1_1 = if (__nb_step > 0) then
85
		(pre Out1_1)
86
	    else false;
87
	pre_Out2_1 = if (__nb_step > 0) then
88
		(pre Out2_1)
89
	    else 0.0;
90
	_isTriggered_clock = _isTriggered;
91
	(Out1_1, Out2_1) = (merge _isTriggered_clock 
92
		(true -> Subsystem1_40_723((In1_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (Trigger_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
93
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
94
tel
95

  
74 96
(*
75 97
Original block name: enable_test2_PP/Subsystem1
76 98
*)
77
node  Subsystem1_96_047_automaton(In1_1 : real;
99
node  Subsystem1_40_723_condExecSS(In1_1 : real;
78 100
	Enable_1 : bool;
79 101
	Trigger_1 : real;
80 102
	_isEnabled : bool;
......
85 107
	Out2_1 : real;);
86 108
var pre_Out1_1 : bool;
87 109
	pre_Out2_1 : real;
110
	_isEnabled_clock : bool clock;
88 111
let
89 112
	pre_Out1_1 = if (__nb_step > 0) then
90 113
		(pre Out1_1)
91 114
	    else false;
92 115
	pre_Out2_1 = if (__nb_step > 0) then
93 116
		(pre Out2_1)
94
	    else 0.000000000000000;
95
	automaton enabled_Subsystem1_96_047
96
	state Active_Subsystem1_96_047:
97
	unless (not _isEnabled) restart Inactive_Subsystem1_96_047
98
	let
99
		automaton triggered_Subsystem1_96_047
100
	state Active_triggered_Subsystem1_96_047:
101
	unless (not _isTriggered) resume Inactive_triggered_Subsystem1_96_047
102
	let
103
		(Out1_1, Out2_1) = Subsystem1_96_047(In1_1, Enable_1, Trigger_1, __time_step, __nb_step);
104
	tel
105

  
106
	state Inactive_triggered_Subsystem1_96_047:
107
	unless _isTriggered resume Active_triggered_Subsystem1_96_047
108
	let
109
		Out1_1 = pre_Out1_1;
110
		Out2_1 = pre_Out2_1;
111
	tel
112

  
113

  
114
	tel
115

  
116
	state Inactive_Subsystem1_96_047:
117
	unless _isEnabled resume Active_Subsystem1_96_047
118
	let
119
		Out1_1 = pre_Out1_1;
120
		Out2_1 = pre_Out2_1;
121
	tel
122

  
123

  
117
	    else 0.0;
118
	_isEnabled_clock = _isEnabled;
119
	(Out1_1, Out2_1) = (merge _isEnabled_clock 
120
		(true -> Subsystem1_40_723_triggeredSS((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
121
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
124 122
tel
125 123

  
126 124
(*
127 125
Original block name: enable_test2_PP/Subsystem1
128 126
*)
129
node  Subsystem1_96_047(In1_1 : real;
127
node  Subsystem1_40_723(In1_1 : real;
130 128
	Enable_1 : bool;
131 129
	Trigger_1 : real;
132 130
	__time_step : real;
......
138 136
	LogicalOperator_1 : bool;
139 137
let
140 138
	Add_1 = 0.0 + Trigger_1 + In1_1;
141
	CompareToZero_1 = CompareToZero_101_043(Add_1, __time_step, __nb_step);
139
	CompareToZero_1 = CompareToZero_54_666(Add_1, __time_step, __nb_step);
142 140
	LogicalOperator_1 = ( CompareToZero_1 and Enable_1 );
143 141
	Out1_1 = LogicalOperator_1;
144 142
	Out2_1 = Add_1;
145 143
tel
146 144

  
147 145
(*
148
Original block name: enable_test2_PP/Subsystem2/CompareToZero
146
Original block name: enable_test2_PP/Subsystem2/Compare
147
To Zero
149 148
*)
150
node  CompareToZero_120_052(u_1 : real;
149
node  CompareToZero_88_362(u_1 : real;
151 150
	__time_step : real;
152 151
	__nb_step : int;)
153 152
returns(y_1 : bool;);
......
155 154
	Constant_1 : real;
156 155
let
157 156
	Compare_1 = (u_1 <= Constant_1);
158
	Constant_1 = 0.000000000000000;
157
	Constant_1 = 0.0;
159 158
	y_1 = Compare_1;
160 159
tel
161 160

  
161
node  Subsystem2_83_387_triggeredSS(In1_1 : real;
162
	Enable_1 : bool;
163
	Trigger_1 : real;
164
	_isEnabled : bool;
165
	_isTriggered : bool;
166
	__time_step : real;
167
	__nb_step : int;)
168
returns(Out1_1 : bool;
169
	Out2_1 : real;);
170
var pre_Out1_1 : bool;
171
	pre_Out2_1 : real;
172
	_isTriggered_clock : bool clock;
173
let
174
	pre_Out1_1 = if (__nb_step > 0) then
175
		(pre Out1_1)
176
	    else false;
177
	pre_Out2_1 = if (__nb_step > 0) then
178
		(pre Out2_1)
179
	    else 0.0;
180
	_isTriggered_clock = _isTriggered;
181
	(Out1_1, Out2_1) = (merge _isTriggered_clock 
182
		(true -> Subsystem2_83_387((In1_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (Trigger_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
183
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
184
tel
185

  
162 186
(*
163 187
Original block name: enable_test2_PP/Subsystem2
164 188
*)
165
node  Subsystem2_115_506_automaton(In1_1 : real;
189
node  Subsystem2_83_387_condExecSS(In1_1 : real;
166 190
	Enable_1 : bool;
167 191
	Trigger_1 : real;
168 192
	_isEnabled : bool;
......
173 197
	Out2_1 : real;);
174 198
var pre_Out1_1 : bool;
175 199
	pre_Out2_1 : real;
200
	_isEnabled_clock : bool clock;
176 201
let
177 202
	pre_Out1_1 = if (__nb_step > 0) then
178 203
		(pre Out1_1)
179 204
	    else false;
180 205
	pre_Out2_1 = if (__nb_step > 0) then
181 206
		(pre Out2_1)
182
	    else 0.000000000000000;
183
	automaton enabled_Subsystem2_115_506
184
	state Active_Subsystem2_115_506:
185
	unless (not _isEnabled) restart Inactive_Subsystem2_115_506
186
	let
187
		automaton triggered_Subsystem2_115_506
188
	state Active_triggered_Subsystem2_115_506:
189
	unless (not _isTriggered) resume Inactive_triggered_Subsystem2_115_506
190
	let
191
		(Out1_1, Out2_1) = Subsystem2_115_506(In1_1, Enable_1, Trigger_1, __time_step, __nb_step);
192
	tel
193

  
194
	state Inactive_triggered_Subsystem2_115_506:
195
	unless _isTriggered resume Active_triggered_Subsystem2_115_506
196
	let
197
		Out1_1 = pre_Out1_1;
198
		Out2_1 = pre_Out2_1;
199
	tel
200

  
201

  
202
	tel
203

  
204
	state Inactive_Subsystem2_115_506:
205
	unless _isEnabled restart Active_Subsystem2_115_506
206
	let
207
		Out1_1 = pre_Out1_1;
208
		Out2_1 = pre_Out2_1;
209
	tel
210

  
211

  
207
	    else 0.0;
208
	_isEnabled_clock = _isEnabled;
209
	(Out1_1, Out2_1) = (merge _isEnabled_clock 
210
		(true -> (Subsystem2_83_387_triggeredSS((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
211
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
212 212
tel
213 213

  
214 214
(*
215 215
Original block name: enable_test2_PP/Subsystem2
216 216
*)
217
node  Subsystem2_115_506(In1_1 : real;
217
node  Subsystem2_83_387(In1_1 : real;
218 218
	Enable_1 : bool;
219 219
	Trigger_1 : real;
220 220
	__time_step : real;
......
226 226
	LogicalOperator_1 : bool;
227 227
let
228 228
	Add_1 = 0.0 + Trigger_1 + In1_1;
229
	CompareToZero_1 = CompareToZero_120_052(Add_1, __time_step, __nb_step);
229
	CompareToZero_1 = CompareToZero_88_362(Add_1, __time_step, __nb_step);
230 230
	LogicalOperator_1 = ( CompareToZero_1 and Enable_1 );
231 231
	Out1_1 = LogicalOperator_1;
232 232
	Out2_1 = Add_1;
......
243 243
	Out3_1 : real;
244 244
	Out4_1 : bool;
245 245
	Out5_1 : real;);
246
var ExecutionCond_of_Subsystem0_90_482 : bool;
247
	TriggerCond_of_Subsystem0_90_482 : bool;
248
	EnableCond_of_Subsystem0_90_482 : bool;
246
var ExecutionCond_of_Subsystem0_19_615 : bool;
247
	TriggerCond_of_Subsystem0_19_615 : bool;
248
	EnableCond_of_Subsystem0_19_615 : bool;
249 249
	Subsystem0_1 : real;
250
	ExecutionCond_of_Subsystem1_96_047 : bool;
251
	TriggerCond_of_Subsystem1_96_047 : bool;
252
	EnableCond_of_Subsystem1_96_047 : bool;
250
	ExecutionCond_of_Subsystem1_40_723 : bool;
251
	TriggerCond_of_Subsystem1_40_723 : bool;
252
	EnableCond_of_Subsystem1_40_723 : bool;
253 253
	Subsystem1_1 : bool;
254 254
	Subsystem1_2 : real;
255
	ExecutionCond_of_Subsystem2_115_506 : bool;
256
	TriggerCond_of_Subsystem2_115_506 : bool;
257
	EnableCond_of_Subsystem2_115_506 : bool;
255
	ExecutionCond_of_Subsystem2_83_387 : bool;
256
	TriggerCond_of_Subsystem2_83_387 : bool;
257
	EnableCond_of_Subsystem2_83_387 : bool;
258 258
	Subsystem2_1 : bool;
259 259
	Subsystem2_2 : real;
260 260
	__time_step : real;
261 261
	__nb_step : int;
262 262
let
263
	EnableCond_of_Subsystem0_90_482 = in3_1;
264
	TriggerCond_of_Subsystem0_90_482 = (false -> ((not in3_1) and (pre in3_1)));
265
	ExecutionCond_of_Subsystem0_90_482 = (EnableCond_of_Subsystem0_90_482 and TriggerCond_of_Subsystem0_90_482);
266
	Subsystem0_1 = Subsystem0_90_482_automaton(in2_1, EnableCond_of_Subsystem0_90_482, TriggerCond_of_Subsystem0_90_482, __time_step, __nb_step);
267
	EnableCond_of_Subsystem1_96_047 = in3_1;
268
	TriggerCond_of_Subsystem1_96_047 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
269
	ExecutionCond_of_Subsystem1_96_047 = (EnableCond_of_Subsystem1_96_047 and TriggerCond_of_Subsystem1_96_047);
270
	(Subsystem1_1, Subsystem1_2) = Subsystem1_96_047_automaton(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem1_96_047 then
263
	EnableCond_of_Subsystem0_19_615 = in3_1;
264
	TriggerCond_of_Subsystem0_19_615 = (false -> ((not in3_1) and (pre in3_1)));
265
	ExecutionCond_of_Subsystem0_19_615 = (EnableCond_of_Subsystem0_19_615 and TriggerCond_of_Subsystem0_19_615);
266
	Subsystem0_1 = Subsystem0_19_615_condExecSS(in2_1, EnableCond_of_Subsystem0_19_615, TriggerCond_of_Subsystem0_19_615, __time_step, __nb_step);
267
	EnableCond_of_Subsystem1_40_723 = in3_1;
268
	TriggerCond_of_Subsystem1_40_723 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
269
	ExecutionCond_of_Subsystem1_40_723 = (EnableCond_of_Subsystem1_40_723 and TriggerCond_of_Subsystem1_40_723);
270
	(Subsystem1_1, Subsystem1_2) = Subsystem1_40_723_condExecSS(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem1_40_723 then
271 271
		if (false -> (in3_1 and (not (pre in3_1)))) then
272 272
		1.0
273 273
	    else (- 1.0)
274
	    else 0.0), EnableCond_of_Subsystem1_96_047, TriggerCond_of_Subsystem1_96_047, __time_step, __nb_step);
275
	EnableCond_of_Subsystem2_115_506 = in3_1;
276
	TriggerCond_of_Subsystem2_115_506 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
277
	ExecutionCond_of_Subsystem2_115_506 = (EnableCond_of_Subsystem2_115_506 and TriggerCond_of_Subsystem2_115_506);
278
	(Subsystem2_1, Subsystem2_2) = Subsystem2_115_506_automaton(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem2_115_506 then
274
	    else 0.0), EnableCond_of_Subsystem1_40_723, TriggerCond_of_Subsystem1_40_723, __time_step, __nb_step);
275
	EnableCond_of_Subsystem2_83_387 = in3_1;
276
	TriggerCond_of_Subsystem2_83_387 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
277
	ExecutionCond_of_Subsystem2_83_387 = (EnableCond_of_Subsystem2_83_387 and TriggerCond_of_Subsystem2_83_387);
278
	(Subsystem2_1, Subsystem2_2) = Subsystem2_83_387_condExecSS(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem2_83_387 then
279 279
		if (false -> (in3_1 and (not (pre in3_1)))) then
280 280
		1.0
281 281
	    else (- 1.0)
282
	    else 0.0), EnableCond_of_Subsystem2_115_506, TriggerCond_of_Subsystem2_115_506, __time_step, __nb_step);
282
	    else 0.0), EnableCond_of_Subsystem2_83_387, TriggerCond_of_Subsystem2_83_387, __time_step, __nb_step);
283 283
	Out1_1 = Subsystem0_1;
284 284
	Out2_1 = Subsystem1_1;
285 285
	Out3_1 = Subsystem1_2;
286 286
	Out4_1 = Subsystem2_1;
287 287
	Out5_1 = Subsystem2_2;
288
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
288
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
289 289
	__nb_step = (0 -> ((pre __nb_step) + 1));
290 290
tel
291 291

  

Also available in: Unified diff