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Revision b58cc410 regression_tests/lustre_files/success/Simulink/src_many_files/enable_DTI_PP.LUSTREC.lus

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regression_tests/lustre_files/success/Simulink/src_many_files/enable_DTI_PP.LUSTREC.lus
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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (ToLustre.m)
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-- Time: 03-Dec-2018 22:34:53
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 13:42:54
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node  bool_to_real(x : bool;)
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returns(y : real;);
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let
......
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator
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*)
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node  Discrete_minus_TimeIntegrator_69_270(f_lpar_x_rpar__1 : real;
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node  Discrete_minus_TimeIntegrator_22_136(f_lpar_x_rpar__1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(F_lpar_x_rpar__1 : real;);
......
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	Sum6_1 : real;
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	UnitDelay_1 : real;
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let
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	Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);
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	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
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	Sum6_1 = 0.0 + Sample_1 + UnitDelay_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Sum6_1));
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	UnitDelay_1 = (0.0 -> (pre Sum6_1));
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	F_lpar_x_rpar__1 = UnitDelay_1;
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tel
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator1
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*)
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node  Discrete_minus_TimeIntegrator1_70_296(f_lpar_x_rpar__1 : real;
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node  Discrete_minus_TimeIntegrator1_60_517(f_lpar_x_rpar__1 : real;
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	reset_falling_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
......
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	ne1_1 : bool;
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	zero_1 : real;
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let
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	Constant_1 = 0.000000000000000;
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	Constant_1 = 0.0;
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	DataTypeConversion_1 = bool_to_real(eq0_1);
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	DataTypeConversion1_1 = bool_to_real(ne1_1);
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	Init_1 = 0.000000000000000;
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	Init_1 = 0.0;
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	Product_1 = 1.0 * Init_1 * UnitDelay1_1;
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	Product2_1 = 1.0 * Sum3_1 * DataTypeConversion_1 * DataTypeConversion1_1;
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	Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);
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	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
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	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
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	Sum2_1 = 0.0 + Sum4_1 + Product_1;
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	Sum3_1 = 0.0 - UnitDelay_1 + Init_1;
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	Sum4_1 = 0.0 + UnitDelay_1 + Product2_1;
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	Sum5_1 = 0.0 + UnitDelay_1 + Product_1;
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	Sum6_1 = 0.0 + Sum5_1 + Product2_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.000000000000000 -> (pre Constant_1));
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	UnitDelay_1 = (0.0 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.0 -> (pre Constant_1));
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	UnitDelay2_1 = (false -> (pre reset_falling_1));
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	eq0_1 = (bool_to_real(reset_falling_1) <= zero_1);
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	ne1_1 = (bool_to_real(UnitDelay2_1) > zero_1);
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	zero_1 = 0.000000000000000;
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	zero_1 = 0.0;
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	F_lpar_x_rpar__1 = Sum6_1;
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tel
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator2
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*)
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node  Discrete_minus_TimeIntegrator2_72_059(f_lpar_x_rpar__1 : real;
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node  Discrete_minus_TimeIntegrator2_130_530(f_lpar_x_rpar__1 : real;
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	x0_1 : real;
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	__time_step : real;
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	__nb_step : int;)
......
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	UnitDelay_1 : real;
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	UnitDelay1_1 : real;
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let
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	Constant_1 = 0.000000000000000;
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	Constant_1 = 0.0;
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	Product_1 = 1.0 * x0_1 * UnitDelay1_1;
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	Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);
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	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
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	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
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	Sum2_1 = 0.0 + UnitDelay_1 + Product_1;
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	Sum6_1 = 0.0 + UnitDelay_1 + Product_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.000000000000000 -> (pre Constant_1));
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	UnitDelay_1 = (0.0 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.0 -> (pre Constant_1));
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	F_lpar_x_rpar__1 = Sum6_1;
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tel
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator3
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*)
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node  Discrete_minus_TimeIntegrator3_73_055(f_lpar_x_rpar__1 : real;
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node  Discrete_minus_TimeIntegrator3_159_114(f_lpar_x_rpar__1 : real;
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	reset_level_1 : bool;
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	x0_1 : real;
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	__time_step : real;
......
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	zero_1 : real;
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let
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	Add_1 = 0.0 + Product1_1 + Product2_1;
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	Constant_1 = 0.000000000000000;
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	Constant_1 = 0.0;
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	DataTypeConversion_1 = bool_to_real(ne0_1);
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	DataTypeConversion1_1 = bool_to_real(eq0_1);
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	DataTypeConversion2_1 = bool_to_real(ne1_1);
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	Product_1 = 1.0 * x0_1 * UnitDelay1_1;
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	Product1_1 = 1.0 * Sum3_1 * DataTypeConversion_1;
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	Product2_1 = 1.0 * Sum3_1 * DataTypeConversion1_1 * DataTypeConversion2_1;
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	Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);
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	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
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	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
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	Sum2_1 = 0.0 + Sum4_1 + Product_1;
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	Sum3_1 = 0.0 - UnitDelay_1 + x0_1;
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	Sum4_1 = 0.0 + UnitDelay_1 + Add_1;
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	Sum5_1 = 0.0 + UnitDelay_1 + Product_1;
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	Sum6_1 = 0.0 + Sum5_1 + Add_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.000000000000000 -> (pre Constant_1));
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	UnitDelay_1 = (0.0 -> (pre Sum1_1));
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	UnitDelay1_1 = (1.0 -> (pre Constant_1));
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	UnitDelay2_1 = (false -> (pre reset_level_1));
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	eq0_1 = (bool_to_real(reset_level_1) = zero_1);
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	ne0_1 = (bool_to_real(reset_level_1) <> zero_1);
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	ne1_1 = (bool_to_real(UnitDelay2_1) <> zero_1);
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	zero_1 = 0.000000000000000;
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	zero_1 = 0.0;
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	F_lpar_x_rpar__1 = Sum6_1;
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tel
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4
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*)
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node  EnabledSubsystem4_65_273_automaton(In1_1 : real;
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node  EnabledSubsystem4_18_599_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	_isEnabled : bool;
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	__time_step : real;
......
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	pre_Out2_1 : real;
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	pre_Out3_1 : real;
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	pre_Out4_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.000000000000000;
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	    else 0.0;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.000000000000000;
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	    else 0.0;
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	pre_Out3_1 = if (__nb_step > 0) then
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		(pre Out3_1)
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	    else 0.000000000000000;
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	    else 0.0;
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	pre_Out4_1 = if (__nb_step > 0) then
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		(pre Out4_1)
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	    else 0.000000000000000;
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	automaton enabled_EnabledSubsystem4_65_273
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	state Active_EnabledSubsystem4_65_273:
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	unless (not _isEnabled) restart Inactive_EnabledSubsystem4_65_273
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	let
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		(Out1_1, Out2_1, Out3_1, Out4_1) = EnabledSubsystem4_65_273(In1_1, Enable_1, __time_step, __nb_step);
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	tel
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	state Inactive_EnabledSubsystem4_65_273:
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	unless _isEnabled restart Active_EnabledSubsystem4_65_273
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	let
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		Out1_1 = pre_Out1_1;
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		Out2_1 = pre_Out2_1;
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		Out3_1 = pre_Out3_1;
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		Out4_1 = pre_Out4_1;
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	tel
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1, Out3_1, Out4_1) = (merge _isEnabled_clock 
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		(true -> (EnabledSubsystem4_18_599((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1, pre_Out4_1) when false(_isEnabled_clock)));
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tel
212 200

  
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(*
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Original block name: enable_DTI_PP/EnabledSubsystem4
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*)
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node  EnabledSubsystem4_65_273(In1_1 : real;
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node  EnabledSubsystem4_18_599(In1_1 : real;
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	Enable_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
......
228 216
	Discrete_minus_TimeIntegrator3_1 : real;
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let
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	Add_1 = 0.0 + bool_to_real(Enable_1) + In1_1;
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	Discrete_minus_TimeIntegrator_1 = Discrete_minus_TimeIntegrator_69_270(Add_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator1_1 = Discrete_minus_TimeIntegrator1_70_296(Add_1, Enable_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator2_1 = Discrete_minus_TimeIntegrator2_72_059(Add_1, In1_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator3_1 = Discrete_minus_TimeIntegrator3_73_055(Add_1, Enable_1, In1_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator_1 = Discrete_minus_TimeIntegrator_22_136(Add_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator1_1 = Discrete_minus_TimeIntegrator1_60_517(Add_1, Enable_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator2_1 = Discrete_minus_TimeIntegrator2_130_530(Add_1, In1_1, __time_step, __nb_step);
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	Discrete_minus_TimeIntegrator3_1 = Discrete_minus_TimeIntegrator3_159_114(Add_1, Enable_1, In1_1, __time_step, __nb_step);
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	Out1_1 = Discrete_minus_TimeIntegrator_1;
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	Out2_1 = Discrete_minus_TimeIntegrator1_1;
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	Out3_1 = Discrete_minus_TimeIntegrator2_1;
......
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	Out8_1 : real;
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	Out9_1 : real;
249 237
	Out10_1 : real;);
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var ExecutionCond_of_EnabledSubsystem4_65_273 : bool;
238
var ExecutionCond_of_EnabledSubsystem4_18_599 : bool;
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	EnabledSubsystem4_1 : real;
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	EnabledSubsystem4_2 : real;
253 241
	EnabledSubsystem4_3 : real;
......
255 243
	__time_step : real;
256 244
	__nb_step : int;
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let
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	ExecutionCond_of_EnabledSubsystem4_65_273 = In1_1;
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	(EnabledSubsystem4_1, EnabledSubsystem4_2, EnabledSubsystem4_3, EnabledSubsystem4_4) = EnabledSubsystem4_65_273_automaton(In2_1, In1_1, ExecutionCond_of_EnabledSubsystem4_65_273, __time_step, __nb_step);
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	ExecutionCond_of_EnabledSubsystem4_18_599 = In1_1;
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	(EnabledSubsystem4_1, EnabledSubsystem4_2, EnabledSubsystem4_3, EnabledSubsystem4_4) = EnabledSubsystem4_18_599_condExecSS(In2_1, In1_1, ExecutionCond_of_EnabledSubsystem4_18_599, __time_step, __nb_step);
260 248
	Out7_1 = EnabledSubsystem4_1;
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	Out8_1 = EnabledSubsystem4_2;
262 250
	Out9_1 = EnabledSubsystem4_3;
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	Out10_1 = EnabledSubsystem4_4;
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	__time_step = (0.0 -> ((pre __time_step) + 1.000000000000000));
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	__time_step = (0.0 -> ((pre __time_step) + 1.0));
265 253
	__nb_step = (0 -> ((pre __nb_step) + 1));
266 254
tel
267 255

  

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