Revision b58cc410 regression_tests/lustre_files/success/Simulink/src_many_files/enable_DTI_PP.LUSTREC.lus
regression_tests/lustre_files/success/Simulink/src_many_files/enable_DTI_PP.LUSTREC.lus  

1  1 
 This file has been generated by CoCoSim2. 
2  2  
3 
 Compiler: Lustre compiler 2 (ToLustre.m) 

4 
 Time: 03Dec2018 22:34:53


3 
 Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)


4 
 Time: 20Mar2019 13:42:54


5  5 
node bool_to_real(x : bool;) 
6  6 
returns(y : real;); 
7  7 
let 
...  ...  
13  13 
(* 
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator 
15  15 
*) 
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node Discrete_minus_TimeIntegrator_69_270(f_lpar_x_rpar__1 : real;


16 
node Discrete_minus_TimeIntegrator_22_136(f_lpar_x_rpar__1 : real;


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__time_step : real; 
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__nb_step : int;) 
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returns(F_lpar_x_rpar__1 : real;); 
...  ...  
21  21 
Sum6_1 : real; 
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UnitDelay_1 : real; 
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let 
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Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);


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Sample_1 = (f_lpar_x_rpar__1 * 1.0); 

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Sum6_1 = 0.0 + Sample_1 + UnitDelay_1; 
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UnitDelay_1 = (0.000000000000000 > (pre Sum6_1));


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UnitDelay_1 = (0.0 > (pre Sum6_1)); 

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F_lpar_x_rpar__1 = UnitDelay_1; 
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tel 
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(* 
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator1 
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*) 
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node Discrete_minus_TimeIntegrator1_70_296(f_lpar_x_rpar__1 : real;


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node Discrete_minus_TimeIntegrator1_60_517(f_lpar_x_rpar__1 : real;


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reset_falling_1 : bool; 
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__time_step : real; 
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__nb_step : int;) 
...  ...  
55  55 
ne1_1 : bool; 
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zero_1 : real; 
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let 
58 
Constant_1 = 0.000000000000000;


58 
Constant_1 = 0.0; 

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DataTypeConversion_1 = bool_to_real(eq0_1); 
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DataTypeConversion1_1 = bool_to_real(ne1_1); 
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Init_1 = 0.000000000000000;


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Init_1 = 0.0; 

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Product_1 = 1.0 * Init_1 * UnitDelay1_1; 
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Product2_1 = 1.0 * Sum3_1 * DataTypeConversion_1 * DataTypeConversion1_1; 
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Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);


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Sample_1 = (f_lpar_x_rpar__1 * 1.0); 

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Sum1_1 = 0.0 + Sample_1 + Sum2_1; 
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Sum2_1 = 0.0 + Sum4_1 + Product_1; 
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Sum3_1 = 0.0  UnitDelay_1 + Init_1; 
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Sum4_1 = 0.0 + UnitDelay_1 + Product2_1; 
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Sum5_1 = 0.0 + UnitDelay_1 + Product_1; 
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Sum6_1 = 0.0 + Sum5_1 + Product2_1; 
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UnitDelay_1 = (0.000000000000000 > (pre Sum1_1));


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UnitDelay1_1 = (1.000000000000000 > (pre Constant_1));


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UnitDelay_1 = (0.0 > (pre Sum1_1)); 

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UnitDelay1_1 = (1.0 > (pre Constant_1)); 

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UnitDelay2_1 = (false > (pre reset_falling_1)); 
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eq0_1 = (bool_to_real(reset_falling_1) <= zero_1); 
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ne1_1 = (bool_to_real(UnitDelay2_1) > zero_1); 
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zero_1 = 0.000000000000000;


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zero_1 = 0.0; 

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F_lpar_x_rpar__1 = Sum6_1; 
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tel 
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(* 
81  81 
Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator2 
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*) 
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node Discrete_minus_TimeIntegrator2_72_059(f_lpar_x_rpar__1 : real;


83 
node Discrete_minus_TimeIntegrator2_130_530(f_lpar_x_rpar__1 : real;


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x0_1 : real; 
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__time_step : real; 
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__nb_step : int;) 
...  ...  
94  94 
UnitDelay_1 : real; 
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UnitDelay1_1 : real; 
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let 
97 
Constant_1 = 0.000000000000000;


97 
Constant_1 = 0.0; 

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Product_1 = 1.0 * x0_1 * UnitDelay1_1; 
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Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);


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Sample_1 = (f_lpar_x_rpar__1 * 1.0); 

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Sum1_1 = 0.0 + Sample_1 + Sum2_1; 
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Sum2_1 = 0.0 + UnitDelay_1 + Product_1; 
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Sum6_1 = 0.0 + UnitDelay_1 + Product_1; 
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UnitDelay_1 = (0.000000000000000 > (pre Sum1_1));


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UnitDelay1_1 = (1.000000000000000 > (pre Constant_1));


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UnitDelay_1 = (0.0 > (pre Sum1_1)); 

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UnitDelay1_1 = (1.0 > (pre Constant_1)); 

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F_lpar_x_rpar__1 = Sum6_1; 
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tel 
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(* 
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Original block name: enable_DTI_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator3 
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*) 
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node Discrete_minus_TimeIntegrator3_73_055(f_lpar_x_rpar__1 : real;


111 
node Discrete_minus_TimeIntegrator3_159_114(f_lpar_x_rpar__1 : real;


112  112 
reset_level_1 : bool; 
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x0_1 : real; 
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__time_step : real; 
...  ...  
138  138 
zero_1 : real; 
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let 
140  140 
Add_1 = 0.0 + Product1_1 + Product2_1; 
141 
Constant_1 = 0.000000000000000;


141 
Constant_1 = 0.0; 

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DataTypeConversion_1 = bool_to_real(ne0_1); 
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DataTypeConversion1_1 = bool_to_real(eq0_1); 
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DataTypeConversion2_1 = bool_to_real(ne1_1); 
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Product_1 = 1.0 * x0_1 * UnitDelay1_1; 
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Product1_1 = 1.0 * Sum3_1 * DataTypeConversion_1; 
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Product2_1 = 1.0 * Sum3_1 * DataTypeConversion1_1 * DataTypeConversion2_1; 
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Sample_1 = (f_lpar_x_rpar__1 * 1.000000000000000);


148 
Sample_1 = (f_lpar_x_rpar__1 * 1.0); 

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Sum1_1 = 0.0 + Sample_1 + Sum2_1; 
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Sum2_1 = 0.0 + Sum4_1 + Product_1; 
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Sum3_1 = 0.0  UnitDelay_1 + x0_1; 
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Sum4_1 = 0.0 + UnitDelay_1 + Add_1; 
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Sum5_1 = 0.0 + UnitDelay_1 + Product_1; 
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Sum6_1 = 0.0 + Sum5_1 + Add_1; 
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UnitDelay_1 = (0.000000000000000 > (pre Sum1_1));


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UnitDelay1_1 = (1.000000000000000 > (pre Constant_1));


155 
UnitDelay_1 = (0.0 > (pre Sum1_1)); 

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UnitDelay1_1 = (1.0 > (pre Constant_1)); 

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UnitDelay2_1 = (false > (pre reset_level_1)); 
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eq0_1 = (bool_to_real(reset_level_1) = zero_1); 
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ne0_1 = (bool_to_real(reset_level_1) <> zero_1); 
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ne1_1 = (bool_to_real(UnitDelay2_1) <> zero_1); 
161 
zero_1 = 0.000000000000000;


161 
zero_1 = 0.0; 

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F_lpar_x_rpar__1 = Sum6_1; 
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tel 
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(* 
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Original block name: enable_DTI_PP/EnabledSubsystem4 
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*) 
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node EnabledSubsystem4_65_273_automaton(In1_1 : real;


168 
node EnabledSubsystem4_18_599_condExecSS(In1_1 : real;


169  169 
Enable_1 : bool; 
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_isEnabled : bool; 
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__time_step : real; 
...  ...  
178  178 
pre_Out2_1 : real; 
179  179 
pre_Out3_1 : real; 
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pre_Out4_1 : real; 
181 
_isEnabled_clock : bool clock; 

181  182 
let 
182  183 
pre_Out1_1 = if (__nb_step > 0) then 
183  184 
(pre Out1_1) 
184 
else 0.000000000000000;


185 
else 0.0; 

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pre_Out2_1 = if (__nb_step > 0) then 
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(pre Out2_1) 
187 
else 0.000000000000000;


188 
else 0.0; 

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pre_Out3_1 = if (__nb_step > 0) then 
189  190 
(pre Out3_1) 
190 
else 0.000000000000000;


191 
else 0.0; 

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pre_Out4_1 = if (__nb_step > 0) then 
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(pre Out4_1) 
193 
else 0.000000000000000; 

194 
automaton enabled_EnabledSubsystem4_65_273 

195 
state Active_EnabledSubsystem4_65_273: 

196 
unless (not _isEnabled) restart Inactive_EnabledSubsystem4_65_273 

197 
let 

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(Out1_1, Out2_1, Out3_1, Out4_1) = EnabledSubsystem4_65_273(In1_1, Enable_1, __time_step, __nb_step); 

199 
tel 

200  
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state Inactive_EnabledSubsystem4_65_273: 

202 
unless _isEnabled restart Active_EnabledSubsystem4_65_273 

203 
let 

204 
Out1_1 = pre_Out1_1; 

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Out2_1 = pre_Out2_1; 

206 
Out3_1 = pre_Out3_1; 

207 
Out4_1 = pre_Out4_1; 

208 
tel 

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210  
194 
else 0.0; 

195 
_isEnabled_clock = _isEnabled; 

196 
(Out1_1, Out2_1, Out3_1, Out4_1) = (merge _isEnabled_clock 

197 
(true > (EnabledSubsystem4_18_599((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false > (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 

198 
(false > (pre_Out1_1, pre_Out2_1, pre_Out3_1, pre_Out4_1) when false(_isEnabled_clock))); 

211  199 
tel 
212  200  
213  201 
(* 
214  202 
Original block name: enable_DTI_PP/EnabledSubsystem4 
215  203 
*) 
216 
node EnabledSubsystem4_65_273(In1_1 : real;


204 
node EnabledSubsystem4_18_599(In1_1 : real;


217  205 
Enable_1 : bool; 
218  206 
__time_step : real; 
219  207 
__nb_step : int;) 
...  ...  
228  216 
Discrete_minus_TimeIntegrator3_1 : real; 
229  217 
let 
230  218 
Add_1 = 0.0 + bool_to_real(Enable_1) + In1_1; 
231 
Discrete_minus_TimeIntegrator_1 = Discrete_minus_TimeIntegrator_69_270(Add_1, __time_step, __nb_step);


232 
Discrete_minus_TimeIntegrator1_1 = Discrete_minus_TimeIntegrator1_70_296(Add_1, Enable_1, __time_step, __nb_step);


233 
Discrete_minus_TimeIntegrator2_1 = Discrete_minus_TimeIntegrator2_72_059(Add_1, In1_1, __time_step, __nb_step);


234 
Discrete_minus_TimeIntegrator3_1 = Discrete_minus_TimeIntegrator3_73_055(Add_1, Enable_1, In1_1, __time_step, __nb_step);


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Discrete_minus_TimeIntegrator_1 = Discrete_minus_TimeIntegrator_22_136(Add_1, __time_step, __nb_step);


220 
Discrete_minus_TimeIntegrator1_1 = Discrete_minus_TimeIntegrator1_60_517(Add_1, Enable_1, __time_step, __nb_step);


221 
Discrete_minus_TimeIntegrator2_1 = Discrete_minus_TimeIntegrator2_130_530(Add_1, In1_1, __time_step, __nb_step);


222 
Discrete_minus_TimeIntegrator3_1 = Discrete_minus_TimeIntegrator3_159_114(Add_1, Enable_1, In1_1, __time_step, __nb_step);


235  223 
Out1_1 = Discrete_minus_TimeIntegrator_1; 
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Out2_1 = Discrete_minus_TimeIntegrator1_1; 
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Out3_1 = Discrete_minus_TimeIntegrator2_1; 
...  ...  
247  235 
Out8_1 : real; 
248  236 
Out9_1 : real; 
249  237 
Out10_1 : real;); 
250 
var ExecutionCond_of_EnabledSubsystem4_65_273 : bool;


238 
var ExecutionCond_of_EnabledSubsystem4_18_599 : bool;


251  239 
EnabledSubsystem4_1 : real; 
252  240 
EnabledSubsystem4_2 : real; 
253  241 
EnabledSubsystem4_3 : real; 
...  ...  
255  243 
__time_step : real; 
256  244 
__nb_step : int; 
257  245 
let 
258 
ExecutionCond_of_EnabledSubsystem4_65_273 = In1_1;


259 
(EnabledSubsystem4_1, EnabledSubsystem4_2, EnabledSubsystem4_3, EnabledSubsystem4_4) = EnabledSubsystem4_65_273_automaton(In2_1, In1_1, ExecutionCond_of_EnabledSubsystem4_65_273, __time_step, __nb_step);


246 
ExecutionCond_of_EnabledSubsystem4_18_599 = In1_1;


247 
(EnabledSubsystem4_1, EnabledSubsystem4_2, EnabledSubsystem4_3, EnabledSubsystem4_4) = EnabledSubsystem4_18_599_condExecSS(In2_1, In1_1, ExecutionCond_of_EnabledSubsystem4_18_599, __time_step, __nb_step);


260  248 
Out7_1 = EnabledSubsystem4_1; 
261  249 
Out8_1 = EnabledSubsystem4_2; 
262  250 
Out9_1 = EnabledSubsystem4_3; 
263  251 
Out10_1 = EnabledSubsystem4_4; 
264 
__time_step = (0.0 > ((pre __time_step) + 1.000000000000000));


252 
__time_step = (0.0 > ((pre __time_step) + 1.0)); 

265  253 
__nb_step = (0 > ((pre __nb_step) + 1)); 
266  254 
tel 
267  255 
Also available in: Unified diff