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regression_tests/lustre_files/success/Simulink/src_many_files/EnableBio1_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:33:42
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:38:55
5 5
node  abs_int(x : int;)
6 6
returns(y : int;);
7 7
let
......
30 30
tel
31 31

  
32 32
(*
33
Original block name: EnableBio1_PP/ChangeMode_equal_MMAddtosequence/IncrementStoredInteger
33
Original block name: EnableBio1_PP/ChangeMode_equal_MMAddtosequence/Increment
34
Stored Integer
34 35
*)
35
node  IncrementStoredInteger_108_047(u_1 : int;
36
node  IncrementStoredInteger_48_386(u_1 : int;
36 37
	__time_step : real;
37 38
	__nb_step : int;)
38 39
returns(y_1 : int;);
......
49 50
(*
50 51
Original block name: EnableBio1_PP/ChangeMode_equal_MMAddtosequence
51 52
*)
52
node  ChangeMode_equal_MMAddtosequence_96_045_automaton(mm_flag_1 : int;
53
node  ChangeMode_equal_MMAddtosequence_20_350_condExecSS(mm_flag_1 : int;
53 54
	cmp_cmd_msg_1_BusElem1 : int;
54 55
	cmp_cmd_msg_1_BusElem2 : int;
55 56
	cmp_cmd_msg_1_BusElem3 : int;
......
170 171
	pre_fm_command_1_BusElem37 : int;
171 172
	pre_fm_command_1_BusElem38 : int;
172 173
	pre_fm_command_1_BusElem39 : int;
174
	_isEnabled_clock : bool clock;
173 175
let
174 176
	pre_fm_command_1_BusElem1 = if (__nb_step > 0) then
175 177
		(pre fm_command_1_BusElem1)
......
288 290
	pre_fm_command_1_BusElem39 = if (__nb_step > 0) then
289 291
		(pre fm_command_1_BusElem39)
290 292
	    else 0;
291
	automaton enabled_ChangeMode_equal_MMAddtosequence_96_045
292
	state Active_ChangeMode_equal_MMAddtosequence_96_045:
293
	unless (not _isEnabled) restart Inactive_ChangeMode_equal_MMAddtosequence_96_045
294
	let
295
		(fm_command_1_BusElem1, fm_command_1_BusElem2, fm_command_1_BusElem3, fm_command_1_BusElem4, fm_command_1_BusElem5, fm_command_1_BusElem6, fm_command_1_BusElem7, fm_command_1_BusElem8, fm_command_1_BusElem9, fm_command_1_BusElem10, fm_command_1_BusElem11, fm_command_1_BusElem12, fm_command_1_BusElem13, fm_command_1_BusElem14, fm_command_1_BusElem15, fm_command_1_BusElem16, fm_command_1_BusElem17, fm_command_1_BusElem18, fm_command_1_BusElem19, fm_command_1_BusElem20, fm_command_1_BusElem21, fm_command_1_BusElem22, fm_command_1_BusElem23, fm_command_1_BusElem24, fm_command_1_BusElem25, fm_command_1_BusElem26, fm_command_1_BusElem27, fm_command_1_BusElem28, fm_command_1_BusElem29, fm_command_1_BusElem30, fm_command_1_BusElem31, fm_command_1_BusElem32, fm_command_1_BusElem33, fm_command_1_BusElem34, fm_command_1_BusElem35, fm_command_1_BusElem36, fm_command_1_BusElem37, fm_command_1_BusElem38, fm_command_1_BusElem39) = ChangeMode_equal_MMAddtosequence_96_045(mm_flag_1, cmp_cmd_msg_1_BusElem1, cmp_cmd_msg_1_BusElem2, cmp_cmd_msg_1_BusElem3, cmp_cmd_msg_1_BusElem4, cmp_cmd_msg_1_BusElem5, cmp_cmd_msg_1_BusElem6, cmp_cmd_msg_1_BusElem7, cmp_cmd_msg_1_BusElem8, cmp_cmd_msg_1_BusElem9, cmp_cmd_msg_1_BusElem10, cmp_cmd_msg_1_BusElem11, cmp_cmd_msg_1_BusElem12, cmp_cmd_msg_1_BusElem13, cmp_cmd_msg_1_BusElem14, cmp_cmd_msg_1_BusElem15, cmp_cmd_msg_1_BusElem16, cmp_cmd_msg_1_BusElem17, cmp_cmd_msg_1_BusElem18, cmp_cmd_msg_1_BusElem19, cmp_cmd_msg_1_BusElem20, cmp_cmd_msg_1_BusElem21, cmp_cmd_msg_1_BusElem22, cmp_cmd_msg_1_BusElem23, cmp_cmd_msg_1_BusElem24, cmp_cmd_msg_1_BusElem25, cmp_cmd_msg_1_BusElem26, cmp_cmd_msg_1_BusElem27, cmp_cmd_msg_1_BusElem28, cmp_cmd_msg_1_BusElem29, cmp_cmd_msg_1_BusElem30, cmp_cmd_msg_1_BusElem31, cmp_cmd_msg_1_BusElem32, cmp_cmd_msg_1_BusElem33, cmp_cmd_msg_1_BusElem34, cmp_cmd_msg_1_BusElem35, cmp_cmd_msg_1_BusElem36, cmp_cmd_msg_1_BusElem37, cmp_cmd_msg_1_BusElem38, cmp_cmd_msg_1_BusElem39, __time_step, __nb_step);
296
	tel
297

  
298
	state Inactive_ChangeMode_equal_MMAddtosequence_96_045:
299
	unless _isEnabled resume Active_ChangeMode_equal_MMAddtosequence_96_045
300
	let
301
		fm_command_1_BusElem1 = pre_fm_command_1_BusElem1;
302
		fm_command_1_BusElem2 = pre_fm_command_1_BusElem2;
303
		fm_command_1_BusElem3 = pre_fm_command_1_BusElem3;
304
		fm_command_1_BusElem4 = pre_fm_command_1_BusElem4;
305
		fm_command_1_BusElem5 = pre_fm_command_1_BusElem5;
306
		fm_command_1_BusElem6 = pre_fm_command_1_BusElem6;
307
		fm_command_1_BusElem7 = pre_fm_command_1_BusElem7;
308
		fm_command_1_BusElem8 = pre_fm_command_1_BusElem8;
309
		fm_command_1_BusElem9 = pre_fm_command_1_BusElem9;
310
		fm_command_1_BusElem10 = pre_fm_command_1_BusElem10;
311
		fm_command_1_BusElem11 = pre_fm_command_1_BusElem11;
312
		fm_command_1_BusElem12 = pre_fm_command_1_BusElem12;
313
		fm_command_1_BusElem13 = pre_fm_command_1_BusElem13;
314
		fm_command_1_BusElem14 = pre_fm_command_1_BusElem14;
315
		fm_command_1_BusElem15 = pre_fm_command_1_BusElem15;
316
		fm_command_1_BusElem16 = pre_fm_command_1_BusElem16;
317
		fm_command_1_BusElem17 = pre_fm_command_1_BusElem17;
318
		fm_command_1_BusElem18 = pre_fm_command_1_BusElem18;
319
		fm_command_1_BusElem19 = pre_fm_command_1_BusElem19;
320
		fm_command_1_BusElem20 = pre_fm_command_1_BusElem20;
321
		fm_command_1_BusElem21 = pre_fm_command_1_BusElem21;
322
		fm_command_1_BusElem22 = pre_fm_command_1_BusElem22;
323
		fm_command_1_BusElem23 = pre_fm_command_1_BusElem23;
324
		fm_command_1_BusElem24 = pre_fm_command_1_BusElem24;
325
		fm_command_1_BusElem25 = pre_fm_command_1_BusElem25;
326
		fm_command_1_BusElem26 = pre_fm_command_1_BusElem26;
327
		fm_command_1_BusElem27 = pre_fm_command_1_BusElem27;
328
		fm_command_1_BusElem28 = pre_fm_command_1_BusElem28;
329
		fm_command_1_BusElem29 = pre_fm_command_1_BusElem29;
330
		fm_command_1_BusElem30 = pre_fm_command_1_BusElem30;
331
		fm_command_1_BusElem31 = pre_fm_command_1_BusElem31;
332
		fm_command_1_BusElem32 = pre_fm_command_1_BusElem32;
333
		fm_command_1_BusElem33 = pre_fm_command_1_BusElem33;
334
		fm_command_1_BusElem34 = pre_fm_command_1_BusElem34;
335
		fm_command_1_BusElem35 = pre_fm_command_1_BusElem35;
336
		fm_command_1_BusElem36 = pre_fm_command_1_BusElem36;
337
		fm_command_1_BusElem37 = pre_fm_command_1_BusElem37;
338
		fm_command_1_BusElem38 = pre_fm_command_1_BusElem38;
339
		fm_command_1_BusElem39 = pre_fm_command_1_BusElem39;
340
	tel
341

  
342

  
293
	_isEnabled_clock = _isEnabled;
294
	(fm_command_1_BusElem1, fm_command_1_BusElem2, fm_command_1_BusElem3, fm_command_1_BusElem4, fm_command_1_BusElem5, fm_command_1_BusElem6, fm_command_1_BusElem7, fm_command_1_BusElem8, fm_command_1_BusElem9, fm_command_1_BusElem10, fm_command_1_BusElem11, fm_command_1_BusElem12, fm_command_1_BusElem13, fm_command_1_BusElem14, fm_command_1_BusElem15, fm_command_1_BusElem16, fm_command_1_BusElem17, fm_command_1_BusElem18, fm_command_1_BusElem19, fm_command_1_BusElem20, fm_command_1_BusElem21, fm_command_1_BusElem22, fm_command_1_BusElem23, fm_command_1_BusElem24, fm_command_1_BusElem25, fm_command_1_BusElem26, fm_command_1_BusElem27, fm_command_1_BusElem28, fm_command_1_BusElem29, fm_command_1_BusElem30, fm_command_1_BusElem31, fm_command_1_BusElem32, fm_command_1_BusElem33, fm_command_1_BusElem34, fm_command_1_BusElem35, fm_command_1_BusElem36, fm_command_1_BusElem37, fm_command_1_BusElem38, fm_command_1_BusElem39) = (merge _isEnabled_clock 
295
		(true -> ChangeMode_equal_MMAddtosequence_20_350((mm_flag_1 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem1 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem2 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem3 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem4 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem5 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem6 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem7 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem8 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem9 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem10 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem11 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem12 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem13 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem14 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem15 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem16 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem17 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem18 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem19 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem20 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem21 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem22 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem23 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem24 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem25 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem26 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem27 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem28 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem29 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem30 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem31 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem32 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem33 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem34 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem35 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem36 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem37 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem38 when _isEnabled_clock), (cmp_cmd_msg_1_BusElem39 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
296
		(false -> (pre_fm_command_1_BusElem1, pre_fm_command_1_BusElem2, pre_fm_command_1_BusElem3, pre_fm_command_1_BusElem4, pre_fm_command_1_BusElem5, pre_fm_command_1_BusElem6, pre_fm_command_1_BusElem7, pre_fm_command_1_BusElem8, pre_fm_command_1_BusElem9, pre_fm_command_1_BusElem10, pre_fm_command_1_BusElem11, pre_fm_command_1_BusElem12, pre_fm_command_1_BusElem13, pre_fm_command_1_BusElem14, pre_fm_command_1_BusElem15, pre_fm_command_1_BusElem16, pre_fm_command_1_BusElem17, pre_fm_command_1_BusElem18, pre_fm_command_1_BusElem19, pre_fm_command_1_BusElem20, pre_fm_command_1_BusElem21, pre_fm_command_1_BusElem22, pre_fm_command_1_BusElem23, pre_fm_command_1_BusElem24, pre_fm_command_1_BusElem25, pre_fm_command_1_BusElem26, pre_fm_command_1_BusElem27, pre_fm_command_1_BusElem28, pre_fm_command_1_BusElem29, pre_fm_command_1_BusElem30, pre_fm_command_1_BusElem31, pre_fm_command_1_BusElem32, pre_fm_command_1_BusElem33, pre_fm_command_1_BusElem34, pre_fm_command_1_BusElem35, pre_fm_command_1_BusElem36, pre_fm_command_1_BusElem37, pre_fm_command_1_BusElem38, pre_fm_command_1_BusElem39) when false(_isEnabled_clock)));
343 297
tel
344 298

  
345 299
(*
346 300
Original block name: EnableBio1_PP/ChangeMode_equal_MMAddtosequence
347 301
*)
348
node  ChangeMode_equal_MMAddtosequence_96_045(mm_flag_1 : int;
302
node  ChangeMode_equal_MMAddtosequence_20_350(mm_flag_1 : int;
349 303
	cmp_cmd_msg_1_BusElem1 : int;
350 304
	cmp_cmd_msg_1_BusElem2 : int;
351 305
	cmp_cmd_msg_1_BusElem3 : int;
......
617 571
	Constant2_1 = 1;
618 572
	Constant6_1 = 3;
619 573
	Constant7_1 = 4;
620
	IncrementStoredInteger_1 = IncrementStoredInteger_108_047(BusSelector_1, __time_step, __nb_step);
574
	IncrementStoredInteger_1 = IncrementStoredInteger_48_386(BusSelector_1, __time_step, __nb_step);
621 575
	SetParams_1 = Switch_1;
622 576
	SetParams_2 = Constant1_2;
623 577
	SetParams_3 = Constant1_3;
......
810 764
	BusSelector_33 : int;
811 765
	BusSelector_34 : int;
812 766
	BusSelector_35 : int;
813
	ExecutionCond_of_ChangeMode_equal_MMAddtosequence_96_045 : bool;
767
	ExecutionCond_of_ChangeMode_equal_MMAddtosequence_20_350 : bool;
814 768
	ChangeMode_equal_MMAddtosequence_1_BusElem1 : int;
815 769
	ChangeMode_equal_MMAddtosequence_1_BusElem2 : int;
816 770
	ChangeMode_equal_MMAddtosequence_1_BusElem3 : int;
......
966 920
	BusSelector_33 = ChangeMode_equal_MMAddtosequence_1_BusElem37;
967 921
	BusSelector_34 = ChangeMode_equal_MMAddtosequence_1_BusElem38;
968 922
	BusSelector_35 = ChangeMode_equal_MMAddtosequence_1_BusElem39;
969
	ExecutionCond_of_ChangeMode_equal_MMAddtosequence_96_045 = Enable_1;
970
	(ChangeMode_equal_MMAddtosequence_1_BusElem1, ChangeMode_equal_MMAddtosequence_1_BusElem2, ChangeMode_equal_MMAddtosequence_1_BusElem3, ChangeMode_equal_MMAddtosequence_1_BusElem4, ChangeMode_equal_MMAddtosequence_1_BusElem5, ChangeMode_equal_MMAddtosequence_1_BusElem6, ChangeMode_equal_MMAddtosequence_1_BusElem7, ChangeMode_equal_MMAddtosequence_1_BusElem8, ChangeMode_equal_MMAddtosequence_1_BusElem9, ChangeMode_equal_MMAddtosequence_1_BusElem10, ChangeMode_equal_MMAddtosequence_1_BusElem11, ChangeMode_equal_MMAddtosequence_1_BusElem12, ChangeMode_equal_MMAddtosequence_1_BusElem13, ChangeMode_equal_MMAddtosequence_1_BusElem14, ChangeMode_equal_MMAddtosequence_1_BusElem15, ChangeMode_equal_MMAddtosequence_1_BusElem16, ChangeMode_equal_MMAddtosequence_1_BusElem17, ChangeMode_equal_MMAddtosequence_1_BusElem18, ChangeMode_equal_MMAddtosequence_1_BusElem19, ChangeMode_equal_MMAddtosequence_1_BusElem20, ChangeMode_equal_MMAddtosequence_1_BusElem21, ChangeMode_equal_MMAddtosequence_1_BusElem22, ChangeMode_equal_MMAddtosequence_1_BusElem23, ChangeMode_equal_MMAddtosequence_1_BusElem24, ChangeMode_equal_MMAddtosequence_1_BusElem25, ChangeMode_equal_MMAddtosequence_1_BusElem26, ChangeMode_equal_MMAddtosequence_1_BusElem27, ChangeMode_equal_MMAddtosequence_1_BusElem28, ChangeMode_equal_MMAddtosequence_1_BusElem29, ChangeMode_equal_MMAddtosequence_1_BusElem30, ChangeMode_equal_MMAddtosequence_1_BusElem31, ChangeMode_equal_MMAddtosequence_1_BusElem32, ChangeMode_equal_MMAddtosequence_1_BusElem33, ChangeMode_equal_MMAddtosequence_1_BusElem34, ChangeMode_equal_MMAddtosequence_1_BusElem35, ChangeMode_equal_MMAddtosequence_1_BusElem36, ChangeMode_equal_MMAddtosequence_1_BusElem37, ChangeMode_equal_MMAddtosequence_1_BusElem38, ChangeMode_equal_MMAddtosequence_1_BusElem39) = ChangeMode_equal_MMAddtosequence_96_045_automaton(In1_1, BusCreator_1_BusElem1, BusCreator_1_BusElem2, BusCreator_1_BusElem3, BusCreator_1_BusElem4, BusCreator_1_BusElem5, BusCreator_1_BusElem6, BusCreator_1_BusElem7, BusCreator_1_BusElem8, BusCreator_1_BusElem9, BusCreator_1_BusElem10, BusCreator_1_BusElem11, BusCreator_1_BusElem12, BusCreator_1_BusElem13, BusCreator_1_BusElem14, BusCreator_1_BusElem15, BusCreator_1_BusElem16, BusCreator_1_BusElem17, BusCreator_1_BusElem18, BusCreator_1_BusElem19, BusCreator_1_BusElem20, BusCreator_1_BusElem21, BusCreator_1_BusElem22, BusCreator_1_BusElem23, BusCreator_1_BusElem24, BusCreator_1_BusElem25, BusCreator_1_BusElem26, BusCreator_1_BusElem27, BusCreator_1_BusElem28, BusCreator_1_BusElem29, BusCreator_1_BusElem30, BusCreator_1_BusElem31, BusCreator_1_BusElem32, BusCreator_1_BusElem33, BusCreator_1_BusElem34, BusCreator_1_BusElem35, BusCreator_1_BusElem36, BusCreator_1_BusElem37, BusCreator_1_BusElem38, BusCreator_1_BusElem39, ExecutionCond_of_ChangeMode_equal_MMAddtosequence_96_045, __time_step, __nb_step);
923
	ExecutionCond_of_ChangeMode_equal_MMAddtosequence_20_350 = Enable_1;
924
	(ChangeMode_equal_MMAddtosequence_1_BusElem1, ChangeMode_equal_MMAddtosequence_1_BusElem2, ChangeMode_equal_MMAddtosequence_1_BusElem3, ChangeMode_equal_MMAddtosequence_1_BusElem4, ChangeMode_equal_MMAddtosequence_1_BusElem5, ChangeMode_equal_MMAddtosequence_1_BusElem6, ChangeMode_equal_MMAddtosequence_1_BusElem7, ChangeMode_equal_MMAddtosequence_1_BusElem8, ChangeMode_equal_MMAddtosequence_1_BusElem9, ChangeMode_equal_MMAddtosequence_1_BusElem10, ChangeMode_equal_MMAddtosequence_1_BusElem11, ChangeMode_equal_MMAddtosequence_1_BusElem12, ChangeMode_equal_MMAddtosequence_1_BusElem13, ChangeMode_equal_MMAddtosequence_1_BusElem14, ChangeMode_equal_MMAddtosequence_1_BusElem15, ChangeMode_equal_MMAddtosequence_1_BusElem16, ChangeMode_equal_MMAddtosequence_1_BusElem17, ChangeMode_equal_MMAddtosequence_1_BusElem18, ChangeMode_equal_MMAddtosequence_1_BusElem19, ChangeMode_equal_MMAddtosequence_1_BusElem20, ChangeMode_equal_MMAddtosequence_1_BusElem21, ChangeMode_equal_MMAddtosequence_1_BusElem22, ChangeMode_equal_MMAddtosequence_1_BusElem23, ChangeMode_equal_MMAddtosequence_1_BusElem24, ChangeMode_equal_MMAddtosequence_1_BusElem25, ChangeMode_equal_MMAddtosequence_1_BusElem26, ChangeMode_equal_MMAddtosequence_1_BusElem27, ChangeMode_equal_MMAddtosequence_1_BusElem28, ChangeMode_equal_MMAddtosequence_1_BusElem29, ChangeMode_equal_MMAddtosequence_1_BusElem30, ChangeMode_equal_MMAddtosequence_1_BusElem31, ChangeMode_equal_MMAddtosequence_1_BusElem32, ChangeMode_equal_MMAddtosequence_1_BusElem33, ChangeMode_equal_MMAddtosequence_1_BusElem34, ChangeMode_equal_MMAddtosequence_1_BusElem35, ChangeMode_equal_MMAddtosequence_1_BusElem36, ChangeMode_equal_MMAddtosequence_1_BusElem37, ChangeMode_equal_MMAddtosequence_1_BusElem38, ChangeMode_equal_MMAddtosequence_1_BusElem39) = ChangeMode_equal_MMAddtosequence_20_350_condExecSS(In1_1, BusCreator_1_BusElem1, BusCreator_1_BusElem2, BusCreator_1_BusElem3, BusCreator_1_BusElem4, BusCreator_1_BusElem5, BusCreator_1_BusElem6, BusCreator_1_BusElem7, BusCreator_1_BusElem8, BusCreator_1_BusElem9, BusCreator_1_BusElem10, BusCreator_1_BusElem11, BusCreator_1_BusElem12, BusCreator_1_BusElem13, BusCreator_1_BusElem14, BusCreator_1_BusElem15, BusCreator_1_BusElem16, BusCreator_1_BusElem17, BusCreator_1_BusElem18, BusCreator_1_BusElem19, BusCreator_1_BusElem20, BusCreator_1_BusElem21, BusCreator_1_BusElem22, BusCreator_1_BusElem23, BusCreator_1_BusElem24, BusCreator_1_BusElem25, BusCreator_1_BusElem26, BusCreator_1_BusElem27, BusCreator_1_BusElem28, BusCreator_1_BusElem29, BusCreator_1_BusElem30, BusCreator_1_BusElem31, BusCreator_1_BusElem32, BusCreator_1_BusElem33, BusCreator_1_BusElem34, BusCreator_1_BusElem35, BusCreator_1_BusElem36, BusCreator_1_BusElem37, BusCreator_1_BusElem38, BusCreator_1_BusElem39, ExecutionCond_of_ChangeMode_equal_MMAddtosequence_20_350, __time_step, __nb_step);
971 925
	Constant_1 = 0;
972 926
	Constant1_1 = 1;
973 927
	Constant2_1 = 1;
......
1042 996
	Out2_32 = BusSelector_33;
1043 997
	Out2_33 = BusSelector_34;
1044 998
	Out2_34 = BusSelector_35;
1045
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
999
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
1046 1000
	__nb_step = (0 -> ((pre __nb_step) + 1));
1047 1001
tel
1048 1002

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort1_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:33:57
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:39:33
5 5
(*
6 6
Original block name: EnablePort1_PP/case_held_reset_held
7 7
*)
8
node  case_held_reset_held_41_066_automaton(Cpre_compx_1 : real;
8
node  case_held_reset_held_18_596_condExecSS(Cpre_compx_1 : real;
9 9
	_isEnabled : bool;
10 10
	__time_step : real;
11 11
	__nb_step : int;)
......
13 13
	pre_x_1 : real;);
14 14
var pre_Ccor_x_1 : real;
15 15
	pre_pre_x_1 : real;
16
	_isEnabled_clock : bool clock;
16 17
let
17
	pre_Ccor_x_1 = 0.000000000000000;
18
	pre_Ccor_x_1 = 0.0;
18 19
	pre_pre_x_1 = if (__nb_step > 0) then
19 20
		(pre pre_x_1)
20
	    else 0.000000000000000;
21
	automaton enabled_case_held_reset_held_41_066
22
	state Active_case_held_reset_held_41_066:
23
	unless (not _isEnabled) restart Inactive_case_held_reset_held_41_066
24
	let
25
		(Ccor_x_1, pre_x_1) = case_held_reset_held_41_066(Cpre_compx_1, __time_step, __nb_step);
26
	tel
27

  
28
	state Inactive_case_held_reset_held_41_066:
29
	unless _isEnabled resume Active_case_held_reset_held_41_066
30
	let
31
		Ccor_x_1 = pre_Ccor_x_1;
32
		pre_x_1 = pre_pre_x_1;
33
	tel
34

  
35

  
21
	    else 0.0;
22
	_isEnabled_clock = _isEnabled;
23
	(Ccor_x_1, pre_x_1) = (merge _isEnabled_clock 
24
		(true -> case_held_reset_held_18_596((Cpre_compx_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
25
		(false -> (pre_Ccor_x_1, pre_pre_x_1) when false(_isEnabled_clock)));
36 26
tel
37 27

  
38 28
(*
39 29
Original block name: EnablePort1_PP/case_held_reset_held
40 30
*)
41
node  case_held_reset_held_41_066(Cpre_compx_1 : real;
31
node  case_held_reset_held_18_596(Cpre_compx_1 : real;
42 32
	__time_step : real;
43 33
	__nb_step : int;)
44 34
returns(Ccor_x_1 : real;
......
48 38
	UnitDelay1_1 : real;
49 39
let
50 40
	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
51
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
52
	UnitDelay1_1 = (0.000000000000000 -> (pre Cpre_compx_1));
41
	UnitDelay_1 = (0.0 -> (pre Add_1));
42
	UnitDelay1_1 = (0.0 -> (pre Cpre_compx_1));
53 43
	Ccor_x_1 = Add_1;
54 44
	pre_x_1 = UnitDelay1_1;
55 45
tel
......
61 51
	Enable_1 : real;)
62 52
returns(Out5_1 : real;
63 53
	pre_Out2_1 : real;);
64
var ExecutionCond_of_case_held_reset_held_41_066 : bool;
54
var ExecutionCond_of_case_held_reset_held_18_596 : bool;
65 55
	case_held_reset_held_1 : real;
66 56
	case_held_reset_held_2 : real;
67 57
	__time_step : real;
68 58
	__nb_step : int;
69 59
let
70
	ExecutionCond_of_case_held_reset_held_41_066 = (Enable_1 > 0.0);
71
	(case_held_reset_held_1, case_held_reset_held_2) = case_held_reset_held_41_066_automaton(In1_1, ExecutionCond_of_case_held_reset_held_41_066, __time_step, __nb_step);
60
	ExecutionCond_of_case_held_reset_held_18_596 = (Enable_1 > 0.0);
61
	(case_held_reset_held_1, case_held_reset_held_2) = case_held_reset_held_18_596_condExecSS(In1_1, ExecutionCond_of_case_held_reset_held_18_596, __time_step, __nb_step);
72 62
	Out5_1 = case_held_reset_held_1;
73 63
	pre_Out2_1 = case_held_reset_held_2;
74
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
64
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
75 65
	__nb_step = (0 -> ((pre __nb_step) + 1));
76 66
tel
77 67

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort2_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:34:06
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:40:06
5 5
(*
6 6
Original block name: EnablePort2_PP/case_reset_held_held
7 7
*)
8
node  case_reset_held_held_39_080_automaton(Cpre_compx_1 : real;
8
node  case_reset_held_held_18_596_condExecSS(Cpre_compx_1 : real;
9 9
	_isEnabled : bool;
10 10
	__time_step : real;
11 11
	__nb_step : int;)
......
13 13
	pre_x_1 : real;);
14 14
var pre_Ccor_x_1 : real;
15 15
	pre_pre_x_1 : real;
16
	_isEnabled_clock : bool clock;
16 17
let
17 18
	pre_Ccor_x_1 = if (__nb_step > 0) then
18 19
		(pre Ccor_x_1)
19
	    else 0.000000000000000;
20
	    else 0.0;
20 21
	pre_pre_x_1 = if (__nb_step > 0) then
21 22
		(pre pre_x_1)
22
	    else 0.000000000000000;
23
	automaton enabled_case_reset_held_held_39_080
24
	state Active_case_reset_held_held_39_080:
25
	unless (not _isEnabled) restart Inactive_case_reset_held_held_39_080
26
	let
27
		(Ccor_x_1, pre_x_1) = case_reset_held_held_39_080(Cpre_compx_1, __time_step, __nb_step);
28
	tel
29

  
30
	state Inactive_case_reset_held_held_39_080:
31
	unless _isEnabled restart Active_case_reset_held_held_39_080
32
	let
33
		Ccor_x_1 = pre_Ccor_x_1;
34
		pre_x_1 = pre_pre_x_1;
35
	tel
36

  
37

  
23
	    else 0.0;
24
	_isEnabled_clock = _isEnabled;
25
	(Ccor_x_1, pre_x_1) = (merge _isEnabled_clock 
26
		(true -> (case_reset_held_held_18_596((Cpre_compx_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
27
		(false -> (pre_Ccor_x_1, pre_pre_x_1) when false(_isEnabled_clock)));
38 28
tel
39 29

  
40 30
(*
41 31
Original block name: EnablePort2_PP/case_reset_held_held
42 32
*)
43
node  case_reset_held_held_39_080(Cpre_compx_1 : real;
33
node  case_reset_held_held_18_596(Cpre_compx_1 : real;
44 34
	__time_step : real;
45 35
	__nb_step : int;)
46 36
returns(Ccor_x_1 : real;
......
49 39
	UnitDelay_1 : real;
50 40
let
51 41
	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
52
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
42
	UnitDelay_1 = (0.0 -> (pre Add_1));
53 43
	Ccor_x_1 = Add_1;
54 44
	pre_x_1 = UnitDelay_1;
55 45
tel
......
61 51
	Enable_1 : real;)
62 52
returns(Out6_1 : real;
63 53
	pre_Out3_1 : real;);
64
var ExecutionCond_of_case_reset_held_held_39_080 : bool;
54
var ExecutionCond_of_case_reset_held_held_18_596 : bool;
65 55
	case_reset_held_held_1 : real;
66 56
	case_reset_held_held_2 : real;
67 57
	__time_step : real;
68 58
	__nb_step : int;
69 59
let
70
	ExecutionCond_of_case_reset_held_held_39_080 = (Enable_1 > 0.0);
71
	(case_reset_held_held_1, case_reset_held_held_2) = case_reset_held_held_39_080_automaton(In1_1, ExecutionCond_of_case_reset_held_held_39_080, __time_step, __nb_step);
60
	ExecutionCond_of_case_reset_held_held_18_596 = (Enable_1 > 0.0);
61
	(case_reset_held_held_1, case_reset_held_held_2) = case_reset_held_held_18_596_condExecSS(In1_1, ExecutionCond_of_case_reset_held_held_18_596, __time_step, __nb_step);
72 62
	Out6_1 = case_reset_held_held_1;
73 63
	pre_Out3_1 = case_reset_held_held_2;
74
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
64
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
75 65
	__nb_step = (0 -> ((pre __nb_step) + 1));
76 66
tel
77 67

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort3_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:34:14
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:40:41
5 5
(*
6 6
Original block name: EnablePort3_PP/case_reset_reset_held
7 7
*)
8
node  case_reset_reset_held_39_080_automaton(Cpre_compx_1 : real;
8
node  case_reset_reset_held_18_597_condExecSS(Cpre_compx_1 : real;
9 9
	_isEnabled : bool;
10 10
	__time_step : real;
11 11
	__nb_step : int;)
......
13 13
	pre_x_1 : real;);
14 14
var pre_Ccor_x_1 : real;
15 15
	pre_pre_x_1 : real;
16
	_isEnabled_clock : bool clock;
16 17
let
17
	pre_Ccor_x_1 = 0.000000000000000;
18
	pre_Ccor_x_1 = 0.0;
18 19
	pre_pre_x_1 = if (__nb_step > 0) then
19 20
		(pre pre_x_1)
20
	    else 0.000000000000000;
21
	automaton enabled_case_reset_reset_held_39_080
22
	state Active_case_reset_reset_held_39_080:
23
	unless (not _isEnabled) restart Inactive_case_reset_reset_held_39_080
24
	let
25
		(Ccor_x_1, pre_x_1) = case_reset_reset_held_39_080(Cpre_compx_1, __time_step, __nb_step);
26
	tel
27

  
28
	state Inactive_case_reset_reset_held_39_080:
29
	unless _isEnabled restart Active_case_reset_reset_held_39_080
30
	let
31
		Ccor_x_1 = pre_Ccor_x_1;
32
		pre_x_1 = pre_pre_x_1;
33
	tel
34

  
35

  
21
	    else 0.0;
22
	_isEnabled_clock = _isEnabled;
23
	(Ccor_x_1, pre_x_1) = (merge _isEnabled_clock 
24
		(true -> (case_reset_reset_held_18_597((Cpre_compx_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
25
		(false -> (pre_Ccor_x_1, pre_pre_x_1) when false(_isEnabled_clock)));
36 26
tel
37 27

  
38 28
(*
39 29
Original block name: EnablePort3_PP/case_reset_reset_held
40 30
*)
41
node  case_reset_reset_held_39_080(Cpre_compx_1 : real;
31
node  case_reset_reset_held_18_597(Cpre_compx_1 : real;
42 32
	__time_step : real;
43 33
	__nb_step : int;)
44 34
returns(Ccor_x_1 : real;
......
47 37
	UnitDelay_1 : real;
48 38
let
49 39
	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
50
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
40
	UnitDelay_1 = (0.0 -> (pre Add_1));
51 41
	Ccor_x_1 = Add_1;
52 42
	pre_x_1 = UnitDelay_1;
53 43
tel
......
59 49
	Enable_1 : real;)
60 50
returns(Out7_1 : real;
61 51
	pre_Out4_1 : real;);
62
var ExecutionCond_of_case_reset_reset_held_39_080 : bool;
52
var ExecutionCond_of_case_reset_reset_held_18_597 : bool;
63 53
	case_reset_reset_held_1 : real;
64 54
	case_reset_reset_held_2 : real;
65 55
	__time_step : real;
66 56
	__nb_step : int;
67 57
let
68
	ExecutionCond_of_case_reset_reset_held_39_080 = (Enable_1 > 0.0);
69
	(case_reset_reset_held_1, case_reset_reset_held_2) = case_reset_reset_held_39_080_automaton(In1_1, ExecutionCond_of_case_reset_reset_held_39_080, __time_step, __nb_step);
58
	ExecutionCond_of_case_reset_reset_held_18_597 = (Enable_1 > 0.0);
59
	(case_reset_reset_held_1, case_reset_reset_held_2) = case_reset_reset_held_18_597_condExecSS(In1_1, ExecutionCond_of_case_reset_reset_held_18_597, __time_step, __nb_step);
70 60
	Out7_1 = case_reset_reset_held_1;
71 61
	pre_Out4_1 = case_reset_reset_held_2;
72
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
62
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
73 63
	__nb_step = (0 -> ((pre __nb_step) + 1));
74 64
tel
75 65

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort4_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:34:25
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:41:12
5 5
(*
6 6
Original block name: EnablePort4_PP/case_held_held_held
7 7
*)
8
node  case_held_held_held_45_285_automaton(Cpre_compx_1 : real;
8
node  case_held_held_held_18_597_condExecSS(Cpre_compx_1 : real;
9 9
	Enable_1 : real;
10 10
	_isEnabled : bool;
11 11
	__time_step : real;
......
16 16
var pre_Ccor_x_1 : real;
17 17
	pre_pre_x_1 : real;
18 18
	pre_Out1_1 : real;
19
	_isEnabled_clock : bool clock;
19 20
let
20 21
	pre_Ccor_x_1 = if (__nb_step > 0) then
21 22
		(pre Ccor_x_1)
22
	    else 0.000000000000000;
23
	    else 0.0;
23 24
	pre_pre_x_1 = if (__nb_step > 0) then
24 25
		(pre pre_x_1)
25
	    else 0.000000000000000;
26
	    else 0.0;
26 27
	pre_Out1_1 = if (__nb_step > 0) then
27 28
		(pre Out1_1)
28
	    else 0.000000000000000;
29
	automaton enabled_case_held_held_held_45_285
30
	state Active_case_held_held_held_45_285:
31
	unless (not _isEnabled) restart Inactive_case_held_held_held_45_285
32
	let
33
		(Ccor_x_1, pre_x_1, Out1_1) = case_held_held_held_45_285(Cpre_compx_1, Enable_1, __time_step, __nb_step);
34
	tel
35

  
36
	state Inactive_case_held_held_held_45_285:
37
	unless _isEnabled resume Active_case_held_held_held_45_285
38
	let
39
		Ccor_x_1 = pre_Ccor_x_1;
40
		pre_x_1 = pre_pre_x_1;
41
		Out1_1 = pre_Out1_1;
42
	tel
43

  
44

  
29
	    else 0.0;
30
	_isEnabled_clock = _isEnabled;
31
	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
32
		(true -> case_held_held_held_18_597((Cpre_compx_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
33
		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
45 34
tel
46 35

  
47 36
(*
48 37
Original block name: EnablePort4_PP/case_held_held_held
49 38
*)
50
node  case_held_held_held_45_285(Cpre_compx_1 : real;
39
node  case_held_held_held_18_597(Cpre_compx_1 : real;
51 40
	Enable_1 : real;
52 41
	__time_step : real;
53 42
	__nb_step : int;)
......
59 48
	UnitDelay1_1 : real;
60 49
let
61 50
	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
62
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
63
	UnitDelay1_1 = (0.000000000000000 -> (pre Cpre_compx_1));
51
	UnitDelay_1 = (0.0 -> (pre Add_1));
52
	UnitDelay1_1 = (0.0 -> (pre Cpre_compx_1));
64 53
	Ccor_x_1 = Add_1;
65 54
	pre_x_1 = UnitDelay1_1;
66 55
	Out1_1 = Enable_1;
......
74 63
returns(Out1_1 : real;
75 64
	Out2_1 : real;
76 65
	Out3_1 : real;);
77
var ExecutionCond_of_case_held_held_held_45_285 : bool;
66
var ExecutionCond_of_case_held_held_held_18_597 : bool;
78 67
	case_held_held_held_1 : real;
79 68
	case_held_held_held_2 : real;
80 69
	case_held_held_held_3 : real;
81 70
	__time_step : real;
82 71
	__nb_step : int;
83 72
let
84
	ExecutionCond_of_case_held_held_held_45_285 = (In1_1 > 0.0);
85
	(case_held_held_held_1, case_held_held_held_2, case_held_held_held_3) = case_held_held_held_45_285_automaton(In2_1, In1_1, ExecutionCond_of_case_held_held_held_45_285, __time_step, __nb_step);
73
	ExecutionCond_of_case_held_held_held_18_597 = (In1_1 > 0.0);
74
	(case_held_held_held_1, case_held_held_held_2, case_held_held_held_3) = case_held_held_held_18_597_condExecSS(In2_1, In1_1, ExecutionCond_of_case_held_held_held_18_597, __time_step, __nb_step);
86 75
	Out1_1 = case_held_held_held_1;
87 76
	Out2_1 = case_held_held_held_2;
88 77
	Out3_1 = case_held_held_held_3;
89
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
78
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
90 79
	__nb_step = (0 -> ((pre __nb_step) + 1));
91 80
tel
92 81

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort5_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:34:36
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:41:44
5 5
(*
6 6
Original block name: EnablePort5_PP/Enabled_Counter/Subsystem
7 7
*)
8
node  Subsystem_76_056_automaton(In1_1 : real;
8
node  Subsystem_30_930_condExecSS(In1_1 : real;
9 9
	Enable_1 : real;
10 10
	_isEnabled : bool;
11 11
	__time_step : real;
......
14 14
	Out2_1 : real;);
15 15
var pre_Out1_1 : real;
16 16
	pre_Out2_1 : real;
17
	_isEnabled_clock : bool clock;
17 18
let
18 19
	pre_Out1_1 = if (__nb_step > 0) then
19 20
		(pre Out1_1)
20
	    else 0.000000000000000;
21
	    else 0.0;
21 22
	pre_Out2_1 = if (__nb_step > 0) then
22 23
		(pre Out2_1)
23
	    else 0.000000000000000;
24
	automaton enabled_Subsystem_76_056
25
	state Active_Subsystem_76_056:
26
	unless (not _isEnabled) restart Inactive_Subsystem_76_056
27
	let
28
		(Out1_1, Out2_1) = Subsystem_76_056(In1_1, Enable_1, __time_step, __nb_step);
29
	tel
30

  
31
	state Inactive_Subsystem_76_056:
32
	unless _isEnabled resume Active_Subsystem_76_056
33
	let
34
		Out1_1 = pre_Out1_1;
35
		Out2_1 = pre_Out2_1;
36
	tel
37

  
38

  
24
	    else 0.0;
25
	_isEnabled_clock = _isEnabled;
26
	(Out1_1, Out2_1) = (merge _isEnabled_clock 
27
		(true -> Subsystem_30_930((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
28
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
39 29
tel
40 30

  
41 31
(*
42 32
Original block name: EnablePort5_PP/Enabled_Counter/Subsystem
43 33
*)
44
node  Subsystem_76_056(In1_1 : real;
34
node  Subsystem_30_930(In1_1 : real;
45 35
	Enable_1 : real;
46 36
	__time_step : real;
47 37
	__nb_step : int;)
......
51 41
	UnitDelay_1 : real;
52 42
let
53 43
	Add_1 = 0.0 + In1_1 + UnitDelay_1;
54
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
44
	UnitDelay_1 = (0.0 -> (pre Add_1));
55 45
	Out1_1 = Add_1;
56 46
	Out2_1 = Enable_1;
57 47
tel
......
59 49
(*
60 50
Original block name: EnablePort5_PP/Enabled_Counter
61 51
*)
62
node  Enabled_Counter_70_296_automaton(In1_1 : real;
52
node  Enabled_Counter_18_598_condExecSS(In1_1 : real;
63 53
	_isEnabled : bool;
64 54
	__time_step : real;
65 55
	__nb_step : int;)
......
69 59
var pre_Out1_1 : real;
70 60
	pre_Out2_1 : real;
71 61
	pre_Out3_1 : real;
62
	_isEnabled_clock : bool clock;
72 63
let
73 64
	pre_Out1_1 = if (__nb_step > 0) then
74 65
		(pre Out1_1)
75
	    else 0.000000000000000;
66
	    else 0.0;
76 67
	pre_Out2_1 = if (__nb_step > 0) then
77 68
		(pre Out2_1)
78
	    else 0.000000000000000;
69
	    else 0.0;
79 70
	pre_Out3_1 = if (__nb_step > 0) then
80 71
		(pre Out3_1)
81
	    else 0.000000000000000;
82
	automaton enabled_Enabled_Counter_70_296
83
	state Active_Enabled_Counter_70_296:
84
	unless (not _isEnabled) restart Inactive_Enabled_Counter_70_296
85
	let
86
		(Out1_1, Out2_1, Out3_1) = Enabled_Counter_70_296(In1_1, __time_step, __nb_step);
87
	tel
88

  
89
	state Inactive_Enabled_Counter_70_296:
90
	unless _isEnabled resume Active_Enabled_Counter_70_296
91
	let
92
		Out1_1 = pre_Out1_1;
93
		Out2_1 = pre_Out2_1;
94
		Out3_1 = pre_Out3_1;
95
	tel
96

  
97

  
72
	    else 0.0;
73
	_isEnabled_clock = _isEnabled;
74
	(Out1_1, Out2_1, Out3_1) = (merge _isEnabled_clock 
75
		(true -> Enabled_Counter_18_598((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
76
		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1) when false(_isEnabled_clock)));
98 77
tel
99 78

  
100 79
(*
101 80
Original block name: EnablePort5_PP/Enabled_Counter
102 81
*)
103
node  Enabled_Counter_70_296(In1_1 : real;
82
node  Enabled_Counter_18_598(In1_1 : real;
104 83
	__time_step : real;
105 84
	__nb_step : int;)
106 85
returns(Out1_1 : real;
107 86
	Out2_1 : real;
108 87
	Out3_1 : real;);
109 88
var Add_1 : real;
110
	ExecutionCond_of_Subsystem_76_056 : bool;
89
	ExecutionCond_of_Subsystem_30_930 : bool;
111 90
	Subsystem_1 : real;
112 91
	Subsystem_2 : real;
113 92
	UnitDelay_1 : real;
114 93
let
115 94
	Add_1 = 0.0 + In1_1 + UnitDelay_1;
116
	ExecutionCond_of_Subsystem_76_056 = (In1_1 > 0.0);
117
	(Subsystem_1, Subsystem_2) = Subsystem_76_056_automaton(In1_1, In1_1, ExecutionCond_of_Subsystem_76_056, __time_step, __nb_step);
118
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
95
	ExecutionCond_of_Subsystem_30_930 = (In1_1 > 0.0);
96
	(Subsystem_1, Subsystem_2) = Subsystem_30_930_condExecSS(In1_1, In1_1, ExecutionCond_of_Subsystem_30_930, __time_step, __nb_step);
97
	UnitDelay_1 = (0.0 -> (pre Add_1));
119 98
	Out1_1 = Add_1;
120 99
	Out2_1 = Subsystem_1;
121 100
	Out3_1 = Subsystem_2;
......
129 108
returns(Out1_1 : real;
130 109
	Out2_1 : real;
131 110
	Out3_1 : real;);
132
var ExecutionCond_of_Enabled_Counter_70_296 : bool;
111
var ExecutionCond_of_Enabled_Counter_18_598 : bool;
133 112
	Enabled_Counter_1 : real;
134 113
	Enabled_Counter_2 : real;
135 114
	Enabled_Counter_3 : real;
136 115
	__time_step : real;
137 116
	__nb_step : int;
138 117
let
139
	ExecutionCond_of_Enabled_Counter_70_296 = (Enable_1 > 0.0);
140
	(Enabled_Counter_1, Enabled_Counter_2, Enabled_Counter_3) = Enabled_Counter_70_296_automaton(In1_1, ExecutionCond_of_Enabled_Counter_70_296, __time_step, __nb_step);
118
	ExecutionCond_of_Enabled_Counter_18_598 = (Enable_1 > 0.0);
119
	(Enabled_Counter_1, Enabled_Counter_2, Enabled_Counter_3) = Enabled_Counter_18_598_condExecSS(In1_1, ExecutionCond_of_Enabled_Counter_18_598, __time_step, __nb_step);
141 120
	Out1_1 = Enabled_Counter_1;
142 121
	Out2_1 = Enabled_Counter_2;
143 122
	Out3_1 = Enabled_Counter_3;
144
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
123
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
145 124
	__nb_step = (0 -> ((pre __nb_step) + 1));
146 125
tel
147 126

  
regression_tests/lustre_files/success/Simulink/src_many_files/EnablePort6_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:34:45
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 13:42:16
5 5
(*
6 6
Original block name: EnablePort6_PP/Enabled_Counter/Subsystem
7 7
*)
8
node  Subsystem_76_056_automaton(In1_1 : real;
8
node  Subsystem_30_931_condExecSS(In1_1 : real;
9 9
	Enable_1 : real;
10 10
	_isEnabled : bool;
11 11
	__time_step : real;
......
14 14
	Out2_1 : real;);
15 15
var pre_Out1_1 : real;
16 16
	pre_Out2_1 : real;
17
	_isEnabled_clock : bool clock;
17 18
let
18
	pre_Out1_1 = 1.000000000000000;
19
	pre_Out2_1 = 1.000000000000000;
20
	automaton enabled_Subsystem_76_056
21
	state Active_Subsystem_76_056:
22
	unless (not _isEnabled) restart Inactive_Subsystem_76_056
23
	let
24
		(Out1_1, Out2_1) = Subsystem_76_056(In1_1, Enable_1, __time_step, __nb_step);
25
	tel
26

  
27
	state Inactive_Subsystem_76_056:
28
	unless _isEnabled restart Active_Subsystem_76_056
29
	let
30
		Out1_1 = pre_Out1_1;
31
		Out2_1 = pre_Out2_1;
32
	tel
33

  
34

  
19
	pre_Out1_1 = 1.0;
20
	pre_Out2_1 = 1.0;
21
	_isEnabled_clock = _isEnabled;
22
	(Out1_1, Out2_1) = (merge _isEnabled_clock 
23
		(true -> (Subsystem_30_931((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
24
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
35 25
tel
36 26

  
37 27
(*
38 28
Original block name: EnablePort6_PP/Enabled_Counter/Subsystem
39 29
*)
40
node  Subsystem_76_056(In1_1 : real;
30
node  Subsystem_30_931(In1_1 : real;
41 31
	Enable_1 : real;
42 32
	__time_step : real;
43 33
	__nb_step : int;)
......
47 37
	UnitDelay_1 : real;
48 38
let
49 39
	Add_1 = 0.0 + In1_1 + UnitDelay_1;
50
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
40
	UnitDelay_1 = (0.0 -> (pre Add_1));
51 41
	Out1_1 = Add_1;
52 42
	Out2_1 = Enable_1;
53 43
tel
......
55 45
(*
56 46
Original block name: EnablePort6_PP/Enabled_Counter
57 47
*)
58
node  Enabled_Counter_70_296_automaton(In1_1 : real;
48
node  Enabled_Counter_18_598_condExecSS(In1_1 : real;
59 49
	_isEnabled : bool;
60 50
	__time_step : real;
61 51
	__nb_step : int;)
......
65 55
var pre_Out1_1 : real;
66 56
	pre_Out2_1 : real;
67 57
	pre_Out3_1 : real;
58
	_isEnabled_clock : bool clock;
68 59
let
69
	pre_Out1_1 = 1.000000000000000;
70
	pre_Out2_1 = 1.000000000000000;
71
	pre_Out3_1 = 1.000000000000000;
72
	automaton enabled_Enabled_Counter_70_296
73
	state Active_Enabled_Counter_70_296:
74
	unless (not _isEnabled) restart Inactive_Enabled_Counter_70_296
75
	let
76
		(Out1_1, Out2_1, Out3_1) = Enabled_Counter_70_296(In1_1, __time_step, __nb_step);
77
	tel
78

  
79
	state Inactive_Enabled_Counter_70_296:
80
	unless _isEnabled restart Active_Enabled_Counter_70_296
81
	let
82
		Out1_1 = pre_Out1_1;
83
		Out2_1 = pre_Out2_1;
84
		Out3_1 = pre_Out3_1;
85
	tel
86

  
87

  
60
	pre_Out1_1 = 1.0;
61
	pre_Out2_1 = 1.0;
62
	pre_Out3_1 = 1.0;
63
	_isEnabled_clock = _isEnabled;
64
	(Out1_1, Out2_1, Out3_1) = (merge _isEnabled_clock 
65
		(true -> (Enabled_Counter_18_598((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
66
		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1) when false(_isEnabled_clock)));
88 67
tel
89 68

  
90 69
(*
91 70
Original block name: EnablePort6_PP/Enabled_Counter
92 71
*)
93
node  Enabled_Counter_70_296(In1_1 : real;
72
node  Enabled_Counter_18_598(In1_1 : real;
94 73
	__time_step : real;
95 74
	__nb_step : int;)
96 75
returns(Out1_1 : real;
97 76
	Out2_1 : real;
98 77
	Out3_1 : real;);
99 78
var Add_1 : real;
100
	ExecutionCond_of_Subsystem_76_056 : bool;
79
	ExecutionCond_of_Subsystem_30_931 : bool;
101 80
	Subsystem_1 : real;
102 81
	Subsystem_2 : real;
103 82
	UnitDelay_1 : real;
104 83
let
105 84
	Add_1 = 0.0 + In1_1 + UnitDelay_1;
106
	ExecutionCond_of_Subsystem_76_056 = (In1_1 > 0.0);
107
	(Subsystem_1, Subsystem_2) = Subsystem_76_056_automaton(In1_1, In1_1, ExecutionCond_of_Subsystem_76_056, __time_step, __nb_step);
108
	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
85
	ExecutionCond_of_Subsystem_30_931 = (In1_1 > 0.0);
86
	(Subsystem_1, Subsystem_2) = Subsystem_30_931_condExecSS(In1_1, In1_1, ExecutionCond_of_Subsystem_30_931, __time_step, __nb_step);
87
	UnitDelay_1 = (0.0 -> (pre Add_1));
109 88
	Out1_1 = Add_1;
110 89
	Out2_1 = Subsystem_1;
111 90
	Out3_1 = Subsystem_2;
......
119 98
returns(Out1_1 : real;
120 99
	Out2_1 : real;
121 100
	Out3_1 : real;);
122
var ExecutionCond_of_Enabled_Counter_70_296 : bool;
101
var ExecutionCond_of_Enabled_Counter_18_598 : bool;
123 102
	Enabled_Counter_1 : real;
124 103
	Enabled_Counter_2 : real;
125 104
	Enabled_Counter_3 : real;
126 105
	__time_step : real;
127 106
	__nb_step : int;
128 107
let
129
	ExecutionCond_of_Enabled_Counter_70_296 = (Enable_1 > 0.0);
130
	(Enabled_Counter_1, Enabled_Counter_2, Enabled_Counter_3) = Enabled_Counter_70_296_automaton(In1_1, ExecutionCond_of_Enabled_Counter_70_296, __time_step, __nb_step);
108
	ExecutionCond_of_Enabled_Counter_18_598 = (Enable_1 > 0.0);
109
	(Enabled_Counter_1, Enabled_Counter_2, Enabled_Counter_3) = Enabled_Counter_18_598_condExecSS(In1_1, ExecutionCond_of_Enabled_Counter_18_598, __time_step, __nb_step);
131 110
	Out1_1 = Enabled_Counter_1;
132 111
	Out2_1 = Enabled_Counter_2;
133 112
	Out3_1 = Enabled_Counter_3;
134
	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
113
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
135 114
	__nb_step = (0 -> ((pre __nb_step) + 1));
136 115
tel
137 116

  
regression_tests/lustre_files/success/Simulink/src_many_files/IF_with_EnabledSS_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:05:58
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 19-Mar-2019 21:16:39
5 5
(*
6 6
Original block name: IF_with_EnabledSS_PP/ActionSubsystem1
7 7
*)
8
node  ActionSubsystem1_50_010_automaton(In1_1 : real;
8
node  ActionSubsystem1_8_013_condExecSS(In1_1 : real;
9 9
	_isEnabled : bool;
10 10
	__time_step : real;
11 11
	__nb_step : int;)
12 12
returns(Out1_1 : real;);
13 13
var pre_Out1_1 : real;
14
	_isEnabled_clock : bool clock;
14 15
let
15 16
	pre_Out1_1 = if (__nb_step > 0) then
16 17
		(pre Out1_1)
17
	    else 0.000000000000000;
18
	automaton enabled_ActionSubsystem1_50_010
19
	state Active_ActionSubsystem1_50_010:
20
	unless (not _isEnabled) restart Inactive_ActionSubsystem1_50_010
21
	let
22
		Out1_1 = ActionSubsystem1_50_010(In1_1, __time_step, __nb_step);
23
	tel
24

  
25
	state Inactive_ActionSubsystem1_50_010:
26
	unless _isEnabled restart Active_ActionSubsystem1_50_010
27
	let
28
		Out1_1 = pre_Out1_1;
29
	tel
30

  
31

  
18
	    else 0.0;
19
	_isEnabled_clock = _isEnabled;
20
	Out1_1 = (merge _isEnabled_clock 
21
		(true -> (ActionSubsystem1_8_013((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
22
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
32 23
tel
33 24

  
34 25
(*
35 26
Original block name: IF_with_EnabledSS_PP/ActionSubsystem1
36 27
*)
37
node  ActionSubsystem1_50_010(In1_1 : real;
28
node  ActionSubsystem1_8_013(In1_1 : real;
38 29
	__time_step : real;
39 30
	__nb_step : int;)
40 31
returns(Out1_1 : real;);
41 32
var UnitDelay_1 : real;
42 33
let
43
	UnitDelay_1 = (0.000000000000000 -> (pre In1_1));
34
	UnitDelay_1 = (0.0 -> (pre In1_1));
44 35
	Out1_1 = UnitDelay_1;
45 36
tel
46 37

  
47 38
(*
48 39
Original block name: IF_with_EnabledSS_PP/ActionSubsystem2
49 40
*)
50
node  ActionSubsystem2_57_013_automaton(In1_1 : real;
41
node  ActionSubsystem2_15_018_condExecSS(In1_1 : real;
51 42
	_isEnabled : bool;
52 43
	__time_step : real;
53 44
	__nb_step : int;)
54 45
returns(Out1_1 : real;);
55 46
var pre_Out1_1 : real;
47
	_isEnabled_clock : bool clock;
56 48
let
57 49
	pre_Out1_1 = if (__nb_step > 0) then
58 50
		(pre Out1_1)
59
	    else 0.000000000000000;
60
	automaton enabled_ActionSubsystem2_57_013
61
	state Active_ActionSubsystem2_57_013:
62
	unless (not _isEnabled) restart Inactive_ActionSubsystem2_57_013
63
	let
64
		Out1_1 = ActionSubsystem2_57_013(In1_1, __time_step, __nb_step);
65
	tel
66

  
67
	state Inactive_ActionSubsystem2_57_013:
68
	unless _isEnabled resume Active_ActionSubsystem2_57_013
69
	let
70
		Out1_1 = pre_Out1_1;
71
	tel
72

  
73

  
51
	    else 0.0;
52
	_isEnabled_clock = _isEnabled;
53
	Out1_1 = (merge _isEnabled_clock 
54
		(true -> ActionSubsystem2_15_018((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
55
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
74 56
tel
75 57

  
76 58
(*
77 59
Original block name: IF_with_EnabledSS_PP/ActionSubsystem2
78 60
*)
79
node  ActionSubsystem2_57_013(In1_1 : real;
61
node  ActionSubsystem2_15_018(In1_1 : real;
80 62
	__time_step : real;
81 63
	__nb_step : int;)
82 64
returns(Out1_1 : real;);
83 65
var UnitDelay_1 : real;
84 66
let
85
	UnitDelay_1 = (0.000000000000000 -> (pre In1_1));
67
	UnitDelay_1 = (0.0 -> (pre In1_1));
86 68
	Out1_1 = UnitDelay_1;
87 69
tel
88 70

  
89 71
(*
90 72
Original block name: IF_with_EnabledSS_PP/ActionSubsystem3
91 73
*)
92
node  ActionSubsystem3_64_010_automaton(In1_1 : real;
74
node  ActionSubsystem3_22_022_condExecSS(In1_1 : real;
93 75
	_isEnabled : bool;
94 76
	__time_step : real;
95 77
	__nb_step : int;)
96 78
returns(Out1_1 : real;);
97 79
var pre_Out1_1 : real;
80
	_isEnabled_clock : bool clock;
98 81
let
99 82
	pre_Out1_1 = if (__nb_step > 0) then
100 83
		(pre Out1_1)
101
	    else 0.000000000000000;
102
	automaton enabled_ActionSubsystem3_64_010
103
	state Active_ActionSubsystem3_64_010:
104
	unless (not _isEnabled) restart Inactive_ActionSubsystem3_64_010
105
	let
106
		Out1_1 = ActionSubsystem3_64_010(In1_1, __time_step, __nb_step);
107
	tel
108

  
109
	state Inactive_ActionSubsystem3_64_010:
110
	unless _isEnabled resume Active_ActionSubsystem3_64_010
111
	let
112
		Out1_1 = pre_Out1_1;
113
	tel
114

  
115

  
84
	    else 0.0;
85
	_isEnabled_clock = _isEnabled;
86
	Out1_1 = (merge _isEnabled_clock 
87
		(true -> ActionSubsystem3_22_022((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
88
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
116 89
tel
117 90

  
118 91
(*
119 92
Original block name: IF_with_EnabledSS_PP/ActionSubsystem3
120 93
*)
121
node  ActionSubsystem3_64_010(In1_1 : real;
94
node  ActionSubsystem3_22_022(In1_1 : real;
122 95
	__time_step : real;
123 96
	__nb_step : int;)
124 97
returns(Out1_1 : real;);
125 98
var UnitDelay_1 : real;
126 99
let
127
	UnitDelay_1 = (0.000000000000000 -> (pre In1_1));
100
	UnitDelay_1 = (0.0 -> (pre In1_1));
128 101
	Out1_1 = UnitDelay_1;
129 102
tel
130 103

  
......
141 114
returns(Out1_1 : real;
142 115
	Out2_1 : real;
143 116
	Out3_1 : real;);
144
var ExecutionCond_of_ActionSubsystem1_50_010 : bool;
117
var ExecutionCond_of_ActionSubsystem1_8_013 : bool;
145 118
	ActionSubsystem1_1 : real;
146
	ExecutionCond_of_ActionSubsystem2_57_013 : bool;
119
	ExecutionCond_of_ActionSubsystem2_15_018 : bool;
147 120
	ActionSubsystem2_1 : real;
148
	ExecutionCond_of_ActionSubsystem3_64_010 : bool;
121
	ExecutionCond_of_ActionSubsystem3_22_022 : bool;
149 122
	ActionSubsystem3_1 : real;
150 123
	If2_1 : bool;
151 124
	If2_2 : bool;
......
153 126
	__time_step : real;
154 127
	__nb_step : int;
155 128
let
156
	ExecutionCond_of_ActionSubsystem1_50_010 = If2_1;
157
	ActionSubsystem1_1 = ActionSubsystem1_50_010_automaton(In2_1, ExecutionCond_of_ActionSubsystem1_50_010, __time_step, __nb_step);
158
	ExecutionCond_of_ActionSubsystem2_57_013 = If2_2;
159
	ActionSubsystem2_1 = ActionSubsystem2_57_013_automaton(In2_1, ExecutionCond_of_ActionSubsystem2_57_013, __time_step, __nb_step);
160
	ExecutionCond_of_ActionSubsystem3_64_010 = If2_3;
161
	ActionSubsystem3_1 = ActionSubsystem3_64_010_automaton(In2_1, ExecutionCond_of_ActionSubsystem3_64_010, __time_step, __nb_step);
129
	ExecutionCond_of_ActionSubsystem1_8_013 = If2_1;
130
	ActionSubsystem1_1 = ActionSubsystem1_8_013_condExecSS(In2_1, ExecutionCond_of_ActionSubsystem1_8_013, __time_step, __nb_step);
131
	ExecutionCond_of_ActionSubsystem2_15_018 = If2_2;
132
	ActionSubsystem2_1 = ActionSubsystem2_15_018_condExecSS(In2_1, ExecutionCond_of_ActionSubsystem2_15_018, __time_step, __nb_step);
133
	ExecutionCond_of_ActionSubsystem3_22_022 = If2_3;
134
	ActionSubsystem3_1 = ActionSubsystem3_22_022_condExecSS(In2_1, ExecutionCond_of_ActionSubsystem3_22_022, __time_step, __nb_step);
162 135
	(If2_1, If2_2, If2_3) = if In1_1 > 1 then
163 136
		(true, false, false)
164 137
	    else if In3_3 > 0 then
......
167 140
	Out1_1 = ActionSubsystem1_1;
168 141
	Out2_1 = ActionSubsystem2_1;
169 142
	Out3_1 = ActionSubsystem3_1;
170
	__time_step = (0.0 -> ((pre __time_step) + 0.020000000000000));
143
	__time_step = (0.0 -> ((pre __time_step) + 0.020));
171 144
	__nb_step = (0 -> ((pre __nb_step) + 1));
172 145
tel
173 146

  
regression_tests/lustre_files/success/Simulink/src_many_files/SwitchCase_PP.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 22:14:19
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 20-Mar-2019 11:52:36
5 5
node  abs_int(x : int;)
6 6
returns(y : int;);
7 7
let
......
22 22
(*
23 23
Original block name: SwitchCase_PP/IfActionSubsystem
24 24
*)
25
node  IfActionSubsystem_58_023_automaton(In3_1 : bool;
25
node  IfActionSubsystem_14_054_condExecSS(In3_1 : bool;
26 26
	_isEnabled : bool;
27 27
	__time_step : real;
28 28
	__nb_step : int;)
29 29
returns(Out4_1 : bool;);
30 30
var pre_Out4_1 : bool;
31
	_isEnabled_clock : bool clock;
31 32
let
32 33
	pre_Out4_1 = if (__nb_step > 0) then
33 34
		(pre Out4_1)
34 35
	    else false;
35
	automaton enabled_IfActionSubsystem_58_023
36
	state Active_IfActionSubsystem_58_023:
37
	unless (not _isEnabled) restart Inactive_IfActionSubsystem_58_023
38
	let
39
		Out4_1 = IfActionSubsystem_58_023(In3_1, __time_step, __nb_step);
40
	tel
41

  
42
	state Inactive_IfActionSubsystem_58_023:
43
	unless _isEnabled resume Active_IfActionSubsystem_58_023
44
	let
45
		Out4_1 = pre_Out4_1;
46
	tel
47

  
48

  
36
	_isEnabled_clock = _isEnabled;
37
	Out4_1 = (merge _isEnabled_clock 
38
		(true -> IfActionSubsystem_14_054((In3_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
39
		(false -> (pre_Out4_1) when false(_isEnabled_clock)));
49 40
tel
50 41

  
51 42
(*
52 43
Original block name: SwitchCase_PP/IfActionSubsystem
53 44
*)
54
node  IfActionSubsystem_58_023(In3_1 : bool;
45
node  IfActionSubsystem_14_054(In3_1 : bool;
55 46
	__time_step : real;
56 47
	__nb_step : int;)
57 48
returns(Out4_1 : bool;);
......
62 53
(*
63 54
Original block name: SwitchCase_PP/IfActionSubsystem1
64 55
*)
65
node  IfActionSubsystem1_63_030_automaton(In1_1 : real;
56
node  IfActionSubsystem1_19_527_condExecSS(In1_1 : real;
66 57
	_isEnabled : bool;
67 58
	__time_step : real;
68 59
	__nb_step : int;)
69 60
returns(Out1_1 : real;);
70 61
var pre_Out1_1 : real;
62
	_isEnabled_clock : bool clock;
71 63
let
72 64
	pre_Out1_1 = if (__nb_step > 0) then
73 65
		(pre Out1_1)
74
	    else 0.000000000000000;
75
	automaton enabled_IfActionSubsystem1_63_030
76
	state Active_IfActionSubsystem1_63_030:
77
	unless (not _isEnabled) restart Inactive_IfActionSubsystem1_63_030
78
	let
79
		Out1_1 = IfActionSubsystem1_63_030(In1_1, __time_step, __nb_step);
80
	tel
81

  
82
	state Inactive_IfActionSubsystem1_63_030:
83
	unless _isEnabled resume Active_IfActionSubsystem1_63_030
84
	let
85
		Out1_1 = pre_Out1_1;
86
	tel
87

  
88

  
66
	    else 0.0;
67
	_isEnabled_clock = _isEnabled;
68
	Out1_1 = (merge _isEnabled_clock 
69
		(true -> IfActionSubsystem1_19_527((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
70
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
89 71
tel
90 72

  
91 73
(*
92 74
Original block name: SwitchCase_PP/IfActionSubsystem1
93 75
*)
94
node  IfActionSubsystem1_63_030(In1_1 : real;
76
node  IfActionSubsystem1_19_527(In1_1 : real;
95 77
	__time_step : real;
96 78
	__nb_step : int;)
97 79
returns(Out1_1 : real;);
......
102 84
(*
103 85
Original block name: SwitchCase_PP/IfActionSubsystem2
104 86
*)
105
node  IfActionSubsystem2_68_023_automaton(In1_1 : bool;
87
node  IfActionSubsystem2_24_284_condExecSS(In1_1 : bool;
106 88
	_isEnabled : bool;
107 89
	__time_step : real;
108 90
	__nb_step : int;)
109 91
returns(Out1_1 : bool;);
110 92
var pre_Out1_1 : bool;
93
	_isEnabled_clock : bool clock;
111 94
let
112 95
	pre_Out1_1 = if (__nb_step > 0) then
113 96
		(pre Out1_1)
114 97
	    else false;
115
	automaton enabled_IfActionSubsystem2_68_023
116
	state Active_IfActionSubsystem2_68_023:
117
	unless (not _isEnabled) restart Inactive_IfActionSubsystem2_68_023
118
	let
119
		Out1_1 = IfActionSubsystem2_68_023(In1_1, __time_step, __nb_step);
120
	tel
121

  
122
	state Inactive_IfActionSubsystem2_68_023:
123
	unless _isEnabled resume Active_IfActionSubsystem2_68_023
124
	let
125
		Out1_1 = pre_Out1_1;
126
	tel
127

  
128

  
98
	_isEnabled_clock = _isEnabled;
99
	Out1_1 = (merge _isEnabled_clock 
100
		(true -> IfActionSubsystem2_24_284((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
101
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
129 102
tel
130 103

  
131 104
(*
132 105
Original block name: SwitchCase_PP/IfActionSubsystem2
133 106
*)
134
node  IfActionSubsystem2_68_023(In1_1 : bool;
107
node  IfActionSubsystem2_24_284(In1_1 : bool;
135 108
	__time_step : real;
136 109
	__nb_step : int;)
137 110
returns(Out1_1 : bool;);
......
142 115
(*
143 116
Original block name: SwitchCase_PP/IfActionSubsystem3
144 117
*)
145
node  IfActionSubsystem3_74_022_automaton(In1_1 : real;
118
node  IfActionSubsystem3_29_278_condExecSS(In1_1 : real;
146 119
	_isEnabled : bool;
147 120
	__time_step : real;
148 121
	__nb_step : int;)
149 122
returns(Out1_1 : real;);
150 123
var pre_Out1_1 : real;
124
	_isEnabled_clock : bool clock;
151 125
let
152 126
	pre_Out1_1 = if (__nb_step > 0) then
153 127
		(pre Out1_1)
154
	    else 0.000000000000000;
155
	automaton enabled_IfActionSubsystem3_74_022
156
	state Active_IfActionSubsystem3_74_022:
157
	unless (not _isEnabled) restart Inactive_IfActionSubsystem3_74_022
158
	let
159
		Out1_1 = IfActionSubsystem3_74_022(In1_1, __time_step, __nb_step);
160
	tel
161

  
162
	state Inactive_IfActionSubsystem3_74_022:
163
	unless _isEnabled resume Active_IfActionSubsystem3_74_022
164
	let
165
		Out1_1 = pre_Out1_1;
166
	tel
167

  
168

  
128
	    else 0.0;
129
	_isEnabled_clock = _isEnabled;
130
	Out1_1 = (merge _isEnabled_clock 
131
		(true -> IfActionSubsystem3_29_278((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
132
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
169 133
tel
170 134

  
171 135
(*
172 136
Original block name: SwitchCase_PP/IfActionSubsystem3
173 137
*)
174
node  IfActionSubsystem3_74_022(In1_1 : real;
138
node  IfActionSubsystem3_29_278(In1_1 : real;
175 139
	__time_step : real;
176 140
	__nb_step : int;)
177 141
returns(Out1_1 : real;);
......
190 154
	Out3_1 : bool;
191 155
	Out4_1 : real;);
192 156
var Constant_1 : int;
193
	ExecutionCond_of_IfActionSubsystem_58_023 : bool;
157
	ExecutionCond_of_IfActionSubsystem_14_054 : bool;
194 158
	IfActionSubsystem_1 : bool;
195
	ExecutionCond_of_IfActionSubsystem1_63_030 : bool;
159
	ExecutionCond_of_IfActionSubsystem1_19_527 : bool;
196 160
	IfActionSubsystem1_1 : real;
197
	ExecutionCond_of_IfActionSubsystem2_68_023 : bool;
161
	ExecutionCond_of_IfActionSubsystem2_24_284 : bool;
198 162
	IfActionSubsystem2_1 : bool;
199
	ExecutionCond_of_IfActionSubsystem3_74_022 : bool;
163
	ExecutionCond_of_IfActionSubsystem3_29_278 : bool;
200 164
	IfActionSubsystem3_1 : real;
201 165
	MathFunction_1 : int;
202 166
	SwitchCase_1 : bool;
......
207 171
	__nb_step : int;
208 172
let
209 173
	Constant_1 = 6;
210
	ExecutionCond_of_IfActionSubsystem_58_023 = SwitchCase_1;
211
	IfActionSubsystem_1 = IfActionSubsystem_58_023_automaton(In7_1, ExecutionCond_of_IfActionSubsystem_58_023, __time_step, __nb_step);
212
	ExecutionCond_of_IfActionSubsystem1_63_030 = SwitchCase_4;
213
	IfActionSubsystem1_1 = IfActionSubsystem1_63_030_automaton(In2_1, ExecutionCond_of_IfActionSubsystem1_63_030, __time_step, __nb_step);
214
	ExecutionCond_of_IfActionSubsystem2_68_023 = SwitchCase_2;
215
	IfActionSubsystem2_1 = IfActionSubsystem2_68_023_automaton(In7_1, ExecutionCond_of_IfActionSubsystem2_68_023, __time_step, __nb_step);
216
	ExecutionCond_of_IfActionSubsystem3_74_022 = SwitchCase_3;
217
	IfActionSubsystem3_1 = IfActionSubsystem3_74_022_automaton(In2_1, ExecutionCond_of_IfActionSubsystem3_74_022, __time_step, __nb_step);
174
	ExecutionCond_of_IfActionSubsystem_14_054 = SwitchCase_1;
175
	IfActionSubsystem_1 = IfActionSubsystem_14_054_condExecSS(In7_1, ExecutionCond_of_IfActionSubsystem_14_054, __time_step, __nb_step);
176
	ExecutionCond_of_IfActionSubsystem1_19_527 = SwitchCase_4;
177
	IfActionSubsystem1_1 = IfActionSubsystem1_19_527_condExecSS(In2_1, ExecutionCond_of_IfActionSubsystem1_19_527, __time_step, __nb_step);
178
	ExecutionCond_of_IfActionSubsystem2_24_284 = SwitchCase_2;
179
	IfActionSubsystem2_1 = IfActionSubsystem2_24_284_condExecSS(In7_1, ExecutionCond_of_IfActionSubsystem2_24_284, __time_step, __nb_step);
180
	ExecutionCond_of_IfActionSubsystem3_29_278 = SwitchCase_3;
181
	IfActionSubsystem3_1 = IfActionSubsystem3_29_278_condExecSS(In2_1, ExecutionCond_of_IfActionSubsystem3_29_278, __time_step, __nb_step);
218 182
	MathFunction_1 = mod_int_int(In1_1, Constant_1);
219 183
	(SwitchCase_1, SwitchCase_2, SwitchCase_3, SwitchCase_4) = if MathFunction_1 = 1 then
220 184
		(true, false, false, false)
......
229 193
	Out15_1 = IfActionSubsystem_1;
230 194
	Out3_1 = IfActionSubsystem2_1;
231 195
	Out4_1 = IfActionSubsystem3_1;
232
	__time_step = (0.0 -> ((pre __time_step) + 0.020000000000000));
196
	__time_step = (0.0 -> ((pre __time_step) + 0.020));
233 197
	__nb_step = (0 -> ((pre __nb_step) + 1));
234 198
tel
235 199

  
regression_tests/lustre_files/success/Simulink/src_many_files/TriggeredEnabled_Subsystem2.KIND2.lus
1
-- This file has been generated by CoCoSim2.
2

  
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 12-Mar-2019 21:22:37
5
(*
6
Original block name: TriggeredEnabled_Subsystem2/Enabled_Counter
7
*)
8
node  Enabled_Counter_341_967(In1_1 : real;
9
	__time_step : real;
10
	__nb_step : int;)
11
returns(Out1_1 : real;
12
	Out2_1 : real;);
13
var Add_1 : real;
14
	UnitDelay_1 : real;
15
let
16
	Add_1 = In1_1 + UnitDelay_1;
17
	UnitDelay_1 = (0.0 -> (pre Add_1));
18
	Out1_1 = Add_1;
19
	Out2_1 = UnitDelay_1;
20
tel
21

  
22
node  Enabled_Counter_341_967_triggeredSS(In1_1 : real;
23
	_isEnabled : bool;
24
	_isTriggered : bool;
25
	__time_step : real;
26
	__nb_step : int;)
27
returns(Out1_1 : real;
28
	Out2_1 : real;);
29
var pre_Out1_1 : real;
30
	pre_Out2_1 : real;
31
let
32
	pre_Out1_1 = if (__nb_step > 0) then
33
		(pre Out1_1)
34
	    else 0.0;
35
	pre_Out2_1 = if (__nb_step > 0) then
36
		(pre Out2_1)
37
	    else 0.0;
38
	(Out1_1, Out2_1) = merge(_isTriggered;
39
		 (activate Enabled_Counter_341_967 every _isTriggered)(In1_1, __time_step, __nb_step);
40
		(pre_Out1_1, pre_Out2_1));
41
tel
42

  
43
(*
44
Original block name: TriggeredEnabled_Subsystem2/Enabled_Counter
45
*)
46
node  Enabled_Counter_341_967_condExecSS(In1_1 : real;
47
	_isEnabled : bool;
48
	_isTriggered : bool;
49
	__time_step : real;
50
	__nb_step : int;)
51
returns(Out1_1 : real;
52
	Out2_1 : real;);
53
var pre_Out1_1 : real;
54
	pre_Out2_1 : real;
55
let
56
	pre_Out1_1 = if (__nb_step > 0) then
57
		(pre Out1_1)
58
	    else 0.0;
59
	pre_Out2_1 = if (__nb_step > 0) then
60
		(pre Out2_1)
61
	    else 0.0;
62
	(Out1_1, Out2_1) = merge(_isEnabled;
63
		 (activate Enabled_Counter_341_967_triggeredSS every _isEnabled restart every (false -> (_isEnabled and (not (pre _isEnabled)))))(In1_1, _isEnabled, _isTriggered, __time_step, __nb_step);
64
		(pre_Out1_1, pre_Out2_1));
65
tel
66

  
67
(*
68
Original block name: TriggeredEnabled_Subsystem2
69
*)
70
node  TriggeredEnabled_Subsystem2(In1_1 : real;
71
	Enable_1 : bool;
72
	Trigger_1 : bool;)
73
returns(Out1_1 : real;
74
	Out2_1 : real;);
75
var ExecutionCond_of_Enabled_Counter_341_967 : bool;
76
	TriggerCond_of_Enabled_Counter_341_967 : bool;
77
	EnableCond_of_Enabled_Counter_341_967 : bool;
78
	Enabled_Counter_1 : real;
79
	Enabled_Counter_2 : real;
80
	__time_step : real;
81
	__nb_step : int;
82
let
83
	EnableCond_of_Enabled_Counter_341_967 = Enable_1;
84
	TriggerCond_of_Enabled_Counter_341_967 = (false -> (Trigger_1 and (not (pre Trigger_1))));
85
	ExecutionCond_of_Enabled_Counter_341_967 = (EnableCond_of_Enabled_Counter_341_967 and TriggerCond_of_Enabled_Counter_341_967);
86
	(Enabled_Counter_1, Enabled_Counter_2) = Enabled_Counter_341_967_condExecSS(In1_1, EnableCond_of_Enabled_Counter_341_967, TriggerCond_of_Enabled_Counter_341_967, __time_step, __nb_step);
87
	Out1_1 = Enabled_Counter_1;
88
	Out2_1 = Enabled_Counter_2;
89
	__time_step = (0.0 -> ((pre __time_step) + 1.0));
90
	__nb_step = (0 -> ((pre __nb_step) + 1));
91
tel
92

  
regression_tests/lustre_files/success/Simulink/src_many_files/TriggeredEnabled_Subsystem2.LUSTREC.lus
1 1
-- This file has been generated by CoCoSim2.
2 2

  
3
-- Compiler: Lustre compiler 2 (ToLustre.m)
4
-- Time: 03-Dec-2018 23:08:06
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 12-Mar-2019 22:09:05
5
node  Enabled_Counter_11_121_triggeredSS(In1_1 : real;
6
	_isEnabled : bool;
7
	_isTriggered : bool;
8
	__time_step : real;
9
	__nb_step : int;)
10
returns(Out1_1 : real;
11
	Out2_1 : real;);
12
var pre_Out1_1 : real;
13
	pre_Out2_1 : real;
14
	_isTriggered_clock : bool clock;
15
let
16
	pre_Out1_1 = if (__nb_step > 0) then
17
		(pre Out1_1)
18
	    else 0.0;
19
	pre_Out2_1 = if (__nb_step > 0) then
20
		(pre Out2_1)
21
	    else 0.0;
22
	_isTriggered_clock = _isTriggered;
23
	(Out1_1, Out2_1) = (merge _isTriggered_clock 
24
		(true -> Enabled_Counter_11_121((In1_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
25
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
26
tel
27

  
5 28
(*
6 29
Original block name: TriggeredEnabled_Subsystem2/Enabled_Counter
7 30
*)
8
node  Enabled_Counter_11_121_automaton(In1_1 : real;
31
node  Enabled_Counter_11_121_condExecSS(In1_1 : real;
9 32
	_isEnabled : bool;
10 33
	_isTriggered : bool;
11 34
	__time_step : real;
......
14 37
	Out2_1 : real;);
15 38
var pre_Out1_1 : real;
16 39
	pre_Out2_1 : real;
40
	_isEnabled_clock : bool clock;
17 41
let
18 42
	pre_Out1_1 = if (__nb_step > 0) then
19 43
		(pre Out1_1)
20
	    else 0.000000000000000;
44
	    else 0.0;
21 45
	pre_Out2_1 = if (__nb_step > 0) then
22 46
		(pre Out2_1)
23
	    else 0.000000000000000;
24
	automaton enabled_Enabled_Counter_11_121
25
	state Active_Enabled_Counter_11_121:
26
	unless (not _isEnabled) restart Inactive_Enabled_Counter_11_121
27
	let
28
		automaton triggered_Enabled_Counter_11_121
29
	state Active_triggered_Enabled_Counter_11_121:
30
	unless (not _isTriggered) resume Inactive_triggered_Enabled_Counter_11_121
31
	let
32
		(Out1_1, Out2_1) = Enabled_Counter_11_121(In1_1, __time_step, __nb_step);
33
	tel
34

  
35
	state Inactive_triggered_Enabled_Counter_11_121:
36
	unless _isTriggered resume Active_triggered_Enabled_Counter_11_121
37
	let
38
		Out1_1 = pre_Out1_1;
39
		Out2_1 = pre_Out2_1;
40
	tel
41

  
42

  
43
	tel
44

  
45
	state Inactive_Enabled_Counter_11_121:
46
	unless _isEnabled restart Active_Enabled_Counter_11_121
47
	let
48
		Out1_1 = pre_Out1_1;
49
		Out2_1 = pre_Out2_1;
50
	tel
51

  
52

  
47
	    else 0.0;
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