Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / stage_claude / base3_event.vhd @ 9bb9b710

History | View | Annotate | Download (1.22 KB)

1

    
2
library ieee;
3
use ieee.std_logic_1164.all;
4

    
5
entity top_base3_correct is
6
    port (clk: in std_logic);
7
end top_base3_correct;
8

    
9
-- Definitions of 'event; 'active...
10
-- https://www.ics.uci.edu/~jmoorkan/vhdlref/attrib.html
11

    
12
-- Rising_edge in if condition
13
-- https://electronics.stackexchange.com/questions/174801/what-is-the-use-of-event-in-vhdl?answertab=votes#tab-top
14

    
15
architecture beh_base3_correct of top_base3_correct is
16
  signal S,O : integer := 0;
17
  signal t, t2: integer := 0;
18
begin
19
  procS: process (clk, O)
20
  begin
21
    if (rising_edge(clk) or O'event) then
22
      S <= O + 1;
23
    end if;
24
    t <= t2 + 1;
25
  end process;
26
 
27
  procR: process (clk, S)
28
  begin
29
    if (rising_edge(clk)) then
30
      O <= S - 1;
31
    end if;
32
    t2 <= t + 1;
33
  end process;
34
end beh_base3_correct;
35

    
36
library ieee;
37
use ieee.std_logic_1164.all;
38
use work.top_base3_correct;
39

    
40
entity top_correct is
41
end top_correct;
42

    
43
architecture test_bench of top_correct is
44
  signal clk: std_logic;
45
begin
46
  inst: entity work.top_base3_correct(beh_base3_correct) port map (clk);
47
    clk <= '0', '1' after 5 ps, '0' after 6 ps, 
48
              '1' after 15 ps, '0' after 16 ps, 
49
              '1' after 25 ps, '0' after 26 ps, 
50
              '1' after 35 ps, '0' after 36 ps;
51
end test_bench;