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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_trigger_test / trigger_test.lus @ 6c3ea955

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-- This file has been generated by cocoSim
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-- System nodes
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node trigger_test_TriggeredSubsystem9 (In1_1_1 : real; In1_1_2 : real; In1_1_3 : real; trigger_test_TriggeredSubsystem9_Trigger_1_1: bool; trigger_test_TriggeredSubsystem9_Trigger_pre_1_1: bool)
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returns (Out1_1_1 : real; Out1_1_2 : real; Out1_1_3 : real); 
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var
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	Trigger_1_1 : real;
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	Add_1_1 : real; Add_1_2 : real; Add_1_3 : real;
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let 
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	Trigger_1_1 = if trigger_test_TriggeredSubsystem9_Trigger_pre_1_1 and not(trigger_test_TriggeredSubsystem9_Trigger_1_1) then -1.0 else 1.0;
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	Add_1_1 = Trigger_1_1 + In1_1_1;
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	Add_1_2 = Trigger_1_1 + In1_1_2;
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	Add_1_3 = Trigger_1_1 + In1_1_3;
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	Out1_1_1 = Add_1_1;
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	Out1_1_2 = Add_1_2;
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	Out1_1_3 = Add_1_3;
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node trigger_test_TriggeredSubsystem8 (In1_1_1 : real)
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returns (Out1_1_1 : real); 
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let 
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	Out1_1_1 = In1_1_1;
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node trigger_test_TriggeredSubsystem7 (In1_1_1 : real)
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returns (Out1_1_1 : real); 
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let 
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	Out1_1_1 = In1_1_1;
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node trigger_test_TriggeredSubsystem6 (In1_1_1 : real)
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returns (Out1_1_1 : real); 
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let 
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	Out1_1_1 = In1_1_1;
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node trigger_test_TriggeredSubsystem5 (In1_1_1 : real; trigger_test_TriggeredSubsystem5_Trigger_1_1: int; trigger_test_TriggeredSubsystem5_Trigger_pre_1_1: int)
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returns (Out1_1_1 : real); 
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var
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	Trigger_1_1 : real;
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	Add_1_1 : real;
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let 
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	Trigger_1_1 = if trigger_test_TriggeredSubsystem5_Trigger_pre_1_1 > trigger_test_TriggeredSubsystem5_Trigger_1_1 then -1.0 else 1.0;
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	Add_1_1 = Trigger_1_1 + In1_1_1;
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	Out1_1_1 = Add_1_1;
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node trigger_test_TriggeredSubsystem4 (In1_1_1 : real)
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returns (Out1_1_1 : real); 
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let 
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	Out1_1_1 = In1_1_1;
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node trigger_test_TriggeredSubsystem3 (In1_1_1 : real)
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returns (Out1_1_1 : real); 
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let 
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	Out1_1_1 = In1_1_1;
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node trigger_test_TriggeredSubsystem2 (In1_1_1 : real; trigger_test_TriggeredSubsystem2_Trigger_1_1: bool; trigger_test_TriggeredSubsystem2_Trigger_pre_1_1: bool)
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returns (Out1_1_1 : real); 
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var
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	Trigger_1_1 : real;
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	Add_1_1 : real;
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let 
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	Trigger_1_1 = if trigger_test_TriggeredSubsystem2_Trigger_pre_1_1 and not(trigger_test_TriggeredSubsystem2_Trigger_1_1) then -1.0 else 1.0;
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	Add_1_1 = Trigger_1_1 + In1_1_1;
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	Out1_1_1 = Add_1_1;
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node trigger_test_TriggeredSubsystem1 (In2_1_1 : real)
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returns (Out2_1_1 : real); 
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var
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	Trigger_1_1 : real;
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	Add_1_1 : real;
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let 
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	Trigger_1_1 = -1.0;
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	Add_1_1 = Trigger_1_1 + In2_1_1;
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	Out2_1_1 = Add_1_1;
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node trigger_test_TriggeredSubsystem (In1_1_1 : real)
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returns (Out1_1_1 : bool); 
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var
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	Trigger_1_1 : real;
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	LogicalOperator_1_1 : bool;
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let 
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	Trigger_1_1 = 1.0;
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	LogicalOperator_1_1 = (Trigger_1_1 != 0.0) and (In1_1_1 != 0.0);
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	Out1_1_1 = LogicalOperator_1_1;
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node trigger_test (In1_1_1 : real; In2_1_1 : bool; In3_1_1 : real; In4_1_1 : int; In5_1_1 : real; In6_1_1 : real; In7_1_1 : real; In7_1_2 : real; In7_1_3 : real; In8_1_1 : bool)
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returns (Out1_1_1 : bool;
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	Out2_2_1 : real;
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	Out3_3_1 : real;
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	Out4_4_1 : real;
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	Out5_5_1 : real;
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	Out6_6_1 : real;
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	Out7_7_1 : real;
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	Out8_8_1 : real;
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	Out9_9_1 : real;
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	Out10_10_1 : real; Out10_10_2 : real; Out10_10_3 : real); 
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var
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	TriggeredSubsystem_1_1 : bool;
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	TriggeredSubsystem1_1_1 : real;
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	TriggeredSubsystem2_1_1 : real;
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	TriggeredSubsystem3_1_1 : real;
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	TriggeredSubsystem4_1_1 : real;
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	TriggeredSubsystem5_1_1 : real;
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	TriggeredSubsystem6_1_1 : real;
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	TriggeredSubsystem7_1_1 : real;
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	TriggeredSubsystem8_1_1 : real;
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	TriggeredSubsystem9_1_1 : real; TriggeredSubsystem9_1_2 : real; TriggeredSubsystem9_1_3 : real;
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	i_virtual_local : real;
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	TriggeredSubsystemIn2_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem1In2_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem2In2_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem2pre_In2_1_1: bool;
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	TriggeredSubsystem3In4_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem4In4_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem5In4_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem5pre_In4_1_1: int;
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	TriggeredSubsystem6In6_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem7In6_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem8In6_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem9In8_1_1_cond_str_trigger: bool;
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	TriggeredSubsystem9pre_In8_1_1: bool;
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let 
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	TriggeredSubsystemIn2_1_1_cond_str_trigger = false -> (not(pre In2_1_1) and In2_1_1);
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	TriggeredSubsystem_1_1 = if (TriggeredSubsystemIn2_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem(In1_1_1) else pre TriggeredSubsystem_1_1;
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	TriggeredSubsystem1In2_1_1_cond_str_trigger = false -> (pre(In2_1_1) and not(In2_1_1));
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	TriggeredSubsystem1_1_1 = if (TriggeredSubsystem1In2_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem1(In1_1_1) else pre TriggeredSubsystem1_1_1;
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	TriggeredSubsystem2In2_1_1_cond_str_trigger = false -> (not(pre(In2_1_1) = In2_1_1));
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	TriggeredSubsystem2pre_In2_1_1 = pre(In2_1_1);
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	TriggeredSubsystem2_1_1 = if (TriggeredSubsystem2In2_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem2(In1_1_1, In2_1_1, TriggeredSubsystem2pre_In2_1_1) else pre TriggeredSubsystem2_1_1;
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	TriggeredSubsystem3In4_1_1_cond_str_trigger = false -> (pre(In4_1_1) <= 0 and In4_1_1 > 0);
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	TriggeredSubsystem3_1_1 = if (TriggeredSubsystem3In4_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem3(In3_1_1) else pre TriggeredSubsystem3_1_1;
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	TriggeredSubsystem4In4_1_1_cond_str_trigger = false -> (pre(In4_1_1) > 0 and In4_1_1 <= 0);
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	TriggeredSubsystem4_1_1 = if (TriggeredSubsystem4In4_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem4(In3_1_1) else pre TriggeredSubsystem4_1_1;
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	TriggeredSubsystem5In4_1_1_cond_str_trigger = false -> ((pre(In4_1_1) > 0 and In4_1_1 <= 0) or (pre(In4_1_1) <= 0 and In4_1_1 > 0));
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	TriggeredSubsystem5pre_In4_1_1 = pre(In4_1_1);
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	TriggeredSubsystem5_1_1 = if (TriggeredSubsystem5In4_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem5(In3_1_1, In4_1_1, TriggeredSubsystem5pre_In4_1_1) else pre TriggeredSubsystem5_1_1;
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	TriggeredSubsystem6In6_1_1_cond_str_trigger = false -> (pre(In6_1_1) <= 0.0 and In6_1_1 > 0.0);
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	TriggeredSubsystem6_1_1 = if (TriggeredSubsystem6In6_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem6(In5_1_1) else pre TriggeredSubsystem6_1_1;
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	TriggeredSubsystem7In6_1_1_cond_str_trigger = false -> (pre(In6_1_1) > 0.0 and In6_1_1 <= 0.0);
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	TriggeredSubsystem7_1_1 = if (TriggeredSubsystem7In6_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem7(In5_1_1) else pre TriggeredSubsystem7_1_1;
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	TriggeredSubsystem8In6_1_1_cond_str_trigger = false -> ((pre(In6_1_1) > 0.0 and In6_1_1 <= 0.0) or (pre(In6_1_1) <= 0.0 and In6_1_1 > 0.0));
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	TriggeredSubsystem8_1_1 = if (TriggeredSubsystem8In6_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem8(In5_1_1) else pre TriggeredSubsystem8_1_1;
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	TriggeredSubsystem9In8_1_1_cond_str_trigger = false -> (not(pre(In8_1_1) = In8_1_1));
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	TriggeredSubsystem9pre_In8_1_1 = pre(In8_1_1);
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	(TriggeredSubsystem9_1_1, TriggeredSubsystem9_1_2, TriggeredSubsystem9_1_3) = if (TriggeredSubsystem9In8_1_1_cond_str_trigger) then trigger_test_TriggeredSubsystem9(In7_1_1, In7_1_2, In7_1_3, In8_1_1, TriggeredSubsystem9pre_In8_1_1) else (pre TriggeredSubsystem9_1_1, pre TriggeredSubsystem9_1_2, pre TriggeredSubsystem9_1_3);
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	Out1_1_1 = TriggeredSubsystem_1_1;
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	Out2_2_1 = TriggeredSubsystem1_1_1;
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	Out3_3_1 = TriggeredSubsystem2_1_1;
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	Out4_4_1 = TriggeredSubsystem3_1_1;
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	Out5_5_1 = TriggeredSubsystem4_1_1;
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	Out6_6_1 = TriggeredSubsystem5_1_1;
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	Out7_7_1 = TriggeredSubsystem6_1_1;
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	Out8_8_1 = TriggeredSubsystem7_1_1;
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	Out9_9_1 = TriggeredSubsystem8_1_1;
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	Out10_10_1 = TriggeredSubsystem9_1_1;
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	Out10_10_2 = TriggeredSubsystem9_1_2;
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	Out10_10_3 = TriggeredSubsystem9_1_3;
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	i_virtual_local= 0.0 -> 1.0;
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