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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / valencia / two_counters.vhd @ 489a769e

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library ieee;
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use ieee.std_logic_1164.all;
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entity counter is
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  port (x   : in  boolean;
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        clk : in std_logic;
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        o   : out boolean);
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end counter;
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architecture greycounter of counter is
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  signal a,b: boolean := false;
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begin
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  p: process (clk)
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  begin
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    if (clk'event and clk = '1') then
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      a <= not b;
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      b <= a;
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    end if;
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  end process;
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  o <= a and b;
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end;
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architecture intloopcounter of counter is
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  signal t: integer := 0;
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begin
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  p : process (clk)
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  begin
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    if (clk'event and clk = '1') then
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      if t = 3 then 
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        t <= 0;
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      else
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        t <= t + 1;
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      end if;
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    end if;
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  end process p;
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  o <= t = 2;
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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entity top is
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  port (x     : in  boolean;
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        clk   : in std_logic;
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        ok    : out boolean);
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end top;
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-- Ensures ok;
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architecture top_behav of top is
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  signal b,d: boolean;
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begin
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  gcount: entity work.counter(greycounter) port map (x,clk,b);
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  icount: entity work.counter(intloopcounter) port map (x,clk,d);
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  ok <= b = d;
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end;