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Revision 489a769e vhdl_json/vhdl_files/2-exportOK/valencia/two_counters.vhd

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vhdl_json/vhdl_files/2-exportOK/valencia/two_counters.vhd
2 2
use ieee.std_logic_1164.all;
3 3

  
4 4
entity counter is
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  port (x: in  boolean;
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        o: out boolean);
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  port (x   : in  boolean;
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        clk : in std_logic;
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        o   : out boolean);
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end counter;
8 9

  
9 10
architecture greycounter of counter is
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  signal a,b: boolean := false;
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begin
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  a <= b;
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  b <= a;
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  p: process (clk)
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  begin
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    if (clk'event and clk = '1') then
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      a <= not b;
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      b <= a;
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    end if;
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  end process;
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  o <= a and b;
15 21
end;
16 22

  
17 23
architecture intloopcounter of counter is
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  signal t: integer := 0;
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begin
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  p : process (t)
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  p : process (clk)
21 27
  begin
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    if t = 3
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    then 
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      t <= 0;
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    else 
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      t <= t + 1;
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    if (clk'event and clk = '1') then
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      if t = 3 then 
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        t <= 0;
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      else
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        t <= t + 1;
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      end if;
27 34
    end if;
28 35
  end process p;
29 36
  o <= t = 2;
......
33 40
use ieee.std_logic_1164.all;
34 41

  
35 42
entity top is
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  port (x : in  boolean;
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        ok: out boolean);
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  port (x     : in  boolean;
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        clk   : in std_logic;
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        ok    : out boolean);
38 46
end top;
39 47

  
40 48
-- Ensures ok;
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architecture top_most of top is
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architecture top_behav of top is
42 50
  signal b,d: boolean;
43 51
begin
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  gc: entity work.counter(greycounter)
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        port map (x,b);
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  ilc: entity work.counter(intloopcounter)
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        port map (x,d);
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  gcount: entity work.counter(greycounter) port map (x,clk,b);
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  icount: entity work.counter(intloopcounter) port map (x,clk,d);
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  ok <= b = d;
49 55
end;

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