Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / valencia / two_counters_tb.vhd @ 489a769e

History | View | Annotate | Download (531 Bytes)

1 489a769e Arnaud Dieumegard
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity two_counters_tb is
5
end two_counters_tb;
6
7
architecture behavior of two_counters_tb is
8
  signal x,ok : boolean;
9
  signal clk : std_logic := '0';
10
begin
11
  top_0: entity work.top(top_behav) port map (x,clk,ok);
12
  clk <= '1' after 0.5 ns when clk = '0' else
13
         '0' after 0.5 ns when clk = '1';
14
  process (clk)
15
  begin
16
    x <= false;
17
    assert false 
18
      report "ok = " & boolean'image(ok) & " | clk = " & std_logic'image(clk)
19
      severity note;
20
  end process;
21
end behavior;