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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / valencia / two_counters.vhd @ 47142ed7

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library ieee;
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use ieee.std_logic_1164.all;
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entity counter is
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  port (x: in  boolean;
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        o: out boolean);
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end counter;
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architecture greycounter of counter is
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  signal a,b: boolean := false;
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begin
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  a <= b;
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  b <= a;
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  o <= a and b;
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end;
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architecture intloopcounter of counter is
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  signal t: integer := 0;
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begin
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  p : process (t)
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  begin
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    if t = 3
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    then 
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      t <= 0;
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    else 
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      t <= t + 1;
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    end if;
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  end process p;
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  o <= t = 2;
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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entity top is
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  port (x : in  boolean;
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        ok: out boolean);
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end top;
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-- Ensures ok;
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architecture top_most of top is
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  signal b,d: boolean;
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begin
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  gc: entity work.counter(greycounter)
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        port map (x,b);
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  ilc: entity work.counter(intloopcounter)
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        port map (x,d);
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  ok <= b = d;
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end;