lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / valencia / programmable_pulse_generator.vhd @ 47142ed7
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library ieee; |
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use ieee.std_logic_1164.all; |
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|
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entity ppg is |
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port ( |
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LoadDelay : in integer; |
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LoadLength : in integer; |
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Data : in std_logic_vector (0 to 7); |
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reset : in std_logic; |
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clk : in std_logic; |
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pulse : out std_logic |
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); |
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end ppg; |
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|
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architecture ppg1 of ppg is |
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signal out_pulse : std_logic := '0'; |
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signal in_delay : integer := LoadDelay; |
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signal in_length : integer := LoadLength; |
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begin |
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p : process (reset, clk) |
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begin |
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if (clk'event and clk = '1') |
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then |
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if (reset = '1') |
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then |
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out_pulse <= '0'; |
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in_delay <= LoadDelay; |
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in_length <= LoadLength; |
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else |
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if (in_delay = 0) |
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then |
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if (in_length > 0) |
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then |
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in_length <= in_length - 1; |
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out_pulse <= '1'; |
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else |
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in_length <= LoadLength; |
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in_delay <= LoadDelay; |
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out_pulse <= '0'; |
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end if; |
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else |
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in_delay <= in_delay - 1; |
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end if; |
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end if; |
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end if; |
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end process p; |
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|
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pulse <= out_pulse; |
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end ppg1; |