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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / valencia / d-latch-and-gate-memories.vhd @ 47142ed7

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--- Adapted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15
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-- main entity
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entity reg4 is
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  port (d0, d1, d2, d3, en, clk: in bit; 
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        q0, q1, q2, q3 : out bit );
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end entity reg4;
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-- main archi
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architecture behav of reg4 is
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  begin
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    q1 <= '1';
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    storage: process (d0, d1, d2, d3, en, clk) is
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      variable stored_d0, stored_d1, stored_d2, stored_d3: bit;
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    begin
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      if en = '1' and clk = '1' then
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        stored_d0 := d0;
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        stored_d1 := d1;
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        stored_d2 := d2;
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        stored_d3 := d3;
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      end if;
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      q0 <= stored_d0 after 5 ns;
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      q1 <= stored_d1 after 5 ns;
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      q2 <= stored_d2 after 5 ns;
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      q3 <= stored_d3 after 5 ns;
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    end process storage;
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end architecture behav;
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-- D-latch
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entity d_latch is
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  port (d, clk: in bit; q: out bit);
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end entity d_latch;
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architecture basic of d_latch is
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begin
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  latch_behavior : process (clk, d) is
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  begin
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    if clk = '1' then
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      q <= d after 2 ns;
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    end if;
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  end process latch_behavior;
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end architecture basic;
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-- and-gate
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entity and2 is
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  port (a, b: in bit; y: out bit);
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end entity and2;
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architecture basic of and2 is
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  begin
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  -- and2_behavior: process (a) is
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  and2_behavior: process (a,b) is
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  begin
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    y <= a and b after 2 ns;
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  end process and2_behavior;
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end architecture basic;
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-- Main archi
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architecture struct of reg4 is
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  signal int_clk: bit;
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  signal mem: bit;
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  begin
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    q0 <= d0 and mem;
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    mem <= not d1;
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    q1 <= d2 and (not mem) and d3;
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    bit0: entity work.d_latch(basic)
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    port map (d0, int_clk, q0);
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    bit1: entity work.d_latch(basic)
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    port map (q => q1, d => d1, clk => int_clk);
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    bit2: entity work.d_latch(basic)
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    port map (d2, int_clk, q2);
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    bit3: entity work.d_latch(basic)
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    port map (d3, int_clk, q3);
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    gate: entity work.and2(basic)
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    port map (en, clk, int_clk);
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end architecture struct;