CristalCaveGem » LustreC » Lustrec-Tests

--- Adapted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15

-- main entity

entity reg4 is

  port (d0, d1, d2, d3, en, clk: in bit; 

        q0, q1, q2, q3 : out bit );

end entity reg4;

-- main archi

architecture behav of reg4 is

  begin

    q1 <= '1';

    storage: process (d0, d1, d2, d3, en, clk) is

      variable stored_d0, stored_d1, stored_d2, stored_d3: bit;

    begin

      if en = '1' and clk = '1' then

        stored_d0 := d0;

        stored_d1 := d1;

        stored_d2 := d2;

        stored_d3 := d3;

      end if;

      q0 <= stored_d0 after 5 ns;

      q1 <= stored_d1 after 5 ns;

      q2 <= stored_d2 after 5 ns;

      q3 <= stored_d3 after 5 ns;

    end process storage;

end architecture behav;

-- D-latch

entity d_latch is

  port (d, clk: in bit; q: out bit);

end entity d_latch;

architecture basic of d_latch is

begin

  latch_behavior : process (clk, d) is

  begin

    if clk = '1' then

      q <= d after 2 ns;

    end if;

  end process latch_behavior;

end architecture basic;

-- and-gate

entity and2 is

  port (a, b: in bit; y: out bit);

end entity and2;

architecture basic of and2 is

  begin

  -- and2_behavior: process (a) is

  and2_behavior: process (a,b) is

  begin

    y <= a and b after 2 ns;

  end process and2_behavior;

end architecture basic;

-- Main archi

architecture struct of reg4 is

  signal int_clk: bit;

  signal mem: bit;

  begin

    q0 <= d0 and mem;

    mem <= not d1;

    q1 <= d2 and (not mem) and d3;

    bit0: entity work.d_latch(basic)

    port map (d0, int_clk, q0);

    bit1: entity work.d_latch(basic)

    port map (q => q1, d => d1, clk => int_clk);

    bit2: entity work.d_latch(basic)

    port map (d2, int_clk, q2);

    bit3: entity work.d_latch(basic)

    port map (d3, int_clk, q3);

    gate: entity work.and2(basic)

    port map (en, clk, int_clk);

end architecture struct;