Revision 47142ed7 vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.json
vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.json | ||
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]} |
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, { |
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", { |
17 |
"name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", { |
|
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"name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", { |
|
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"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{ |
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"expr" : [{ |
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"value" : ["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
22 |
"args" : [["EXPRESSION", { |
|
23 |
"args" : [["EXPRESSION", { |
|
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"args" : [["CONSTANT_VALUE", { |
|
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"value" : ["CST_LITERAL", "'1'"]} |
|
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]]} |
|
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]} |
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], ["PROCESS_STATEMENT", { |
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18 | 34 |
"id" : ["IDENTIFIER", "storage"], "PROCESS_DECLARATIVE_PART" : [{ |
19 | 35 |
"declaration" : ["VARIABLE_DECLARATION", { |
20 | 36 |
"names" : [["IDENTIFIER", "stored_d0"], ["IDENTIFIER", "stored_d1"], ["IDENTIFIER", "stored_d2"], ["IDENTIFIER", "stored_d3"]], "typ" : { |
... | ... | |
187 | 203 |
]]} |
188 | 204 |
]} |
189 | 205 |
]} |
190 |
], ["WAIT_STATEMENT"]]}
|
|
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]]} |
|
191 | 207 |
]]} |
192 | 208 |
]} |
193 | 209 |
, { |
... | ... | |
247 | 263 |
]} |
248 | 264 |
]]} |
249 | 265 |
]} |
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], ["WAIT_STATEMENT"]]}
|
|
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]]} |
|
251 | 267 |
]]} |
252 | 268 |
]} |
253 | 269 |
, { |
... | ... | |
297 | 313 |
]]} |
298 | 314 |
]} |
299 | 315 |
]} |
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], ["WAIT_STATEMENT"]]}
|
|
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]]} |
|
301 | 317 |
]]} |
302 | 318 |
]} |
303 | 319 |
, { |
... | ... | |
308 | 324 |
"name" : ["SIMPLE_NAME", "bit"]} |
309 | 325 |
} |
310 | 326 |
]} |
327 |
, { |
|
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"declaration" : ["SIGNAL_DECLARATION", { |
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"names" : [["IDENTIFIER", "mem"]], "typ" : { |
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"name" : ["SIMPLE_NAME", "bit"]} |
|
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} |
|
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]} |
|
311 | 333 |
], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", { |
312 | 334 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{ |
313 | 335 |
"expr" : [{ |
314 | 336 |
"value" : ["EXPRESSION", { |
315 |
"args" : [["EXPRESSION", { |
|
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"id" : "and", "args" : [["EXPRESSION", {
|
|
316 | 338 |
"args" : [["EXPRESSION", { |
317 | 339 |
"args" : [["EXPRESSION", { |
318 |
"id" : "&", "args" : [["EXPRESSION", {
|
|
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"args" : [["EXPRESSION", { |
|
319 | 341 |
"args" : [["CALL", ["SIMPLE_NAME", "d0"]]]} |
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], ["EXPRESSION", { |
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"args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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], ["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
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"args" : [["EXPRESSION", { |
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"args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
|
322 | 350 |
]]} |
323 | 351 |
]]} |
324 | 352 |
]]} |
... | ... | |
327 | 355 |
]} |
328 | 356 |
]} |
329 | 357 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", { |
330 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
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|
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"postponed" : false, "lhs" : ["SIMPLE_NAME", "mem"], "rhs" : [{
|
|
331 | 359 |
"expr" : [{ |
332 | 360 |
"value" : ["EXPRESSION", { |
333 | 361 |
"args" : [["EXPRESSION", { |
334 | 362 |
"args" : [["EXPRESSION", { |
335 | 363 |
"args" : [["EXPRESSION", { |
336 |
"id" : "&", "args" : [["EXPRESSION", { |
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"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
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], ["EXPRESSION", { |
|
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"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]} |
|
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]} |
|
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]} |
|
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], ["CONDITIONAL_SIGNAL_ASSIGNMENT", { |
|
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"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{ |
|
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"expr" : [{ |
|
374 |
"value" : ["EXPRESSION", { |
|
375 |
"id" : "and", "args" : [["EXPRESSION", { |
|
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"id" : "and", "args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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], ["EXPRESSION", { |
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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]]} |
|
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], ["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
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"args" : [["EXPRESSION", { |
|
339 | 405 |
"args" : [["CALL", ["SIMPLE_NAME", "d3"]]]} |
340 | 406 |
]]} |
341 | 407 |
]]} |
... | ... | |
354 | 420 |
]} |
355 | 421 |
], ["COMPONENT_INSTANTIATION_STATEMENT", { |
356 | 422 |
"name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{ |
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"actual_designator" : ["SIMPLE_NAME", "d1"]}
|
|
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"formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
|
|
358 | 424 |
, { |
359 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
|
|
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"formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "d1"]}
|
|
360 | 426 |
, { |
361 |
"actual_designator" : ["SIMPLE_NAME", "q1"]}
|
|
427 |
"formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
|
|
362 | 428 |
]} |
363 | 429 |
], ["COMPONENT_INSTANTIATION_STATEMENT", { |
364 | 430 |
"name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{ |
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