Revision 47142ed7
| vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate-memories.json | ||
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{
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"DESIGN_FILE" : {
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"design_units" : [{
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"contexts" : [], "library" : ["ENTITY_DECLARATION", {
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"name" : ["IDENTIFIER", "reg4"], "ports" : [{
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"names" : [["IDENTIFIER", "d0"], ["IDENTIFIER", "d1"], ["IDENTIFIER", "d2"], ["IDENTIFIER", "d3"], ["IDENTIFIER", "en"], ["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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, {
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"names" : [["IDENTIFIER", "q0"], ["IDENTIFIER", "q1"], ["IDENTIFIER", "q2"], ["IDENTIFIER", "q3"]], "mode" : ["out"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
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]} |
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, {
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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"name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
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"expr" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "'1'"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]} |
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], ["PROCESS_STATEMENT", {
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"id" : ["IDENTIFIER", "storage"], "PROCESS_DECLARATIVE_PART" : [{
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"declaration" : ["VARIABLE_DECLARATION", {
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"names" : [["IDENTIFIER", "stored_d0"], ["IDENTIFIER", "stored_d1"], ["IDENTIFIER", "stored_d2"], ["IDENTIFIER", "stored_d3"]], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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]} |
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], "active_sigs" : [["SIMPLE_NAME", "d0"], ["SIMPLE_NAME", "d1"], ["SIMPLE_NAME", "d2"], ["SIMPLE_NAME", "d3"], ["SIMPLE_NAME", "en"], ["SIMPLE_NAME", "clk"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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"if_cases" : [{
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"if_cond" : ["EXPRESSION", {
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"id" : "and", "args" : [["EXPRESSION", {
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"id" : "=", "args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "en"]]]} |
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]]} |
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]]} |
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], ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "'1'"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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], ["EXPRESSION", {
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"id" : "=", "args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "clk"]]]} |
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]]} |
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]]} |
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], ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "'1'"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]]} |
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], "if_block" : [["VARIABLE_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "stored_d0"], "rhs" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "d0"]]]} |
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]]} |
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]]} |
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]]} |
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]} |
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], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "stored_d1"], "rhs" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
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]]} |
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]]} |
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]]} |
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]} |
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], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "stored_d2"], "rhs" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
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]]} |
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]]} |
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]]} |
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]} |
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], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "stored_d3"], "rhs" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "d3"]]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]]} |
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]} |
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], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "stored_d0"]]]} |
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]]} |
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]]} |
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]]} |
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], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "stored_d1"]]]} |
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]]} |
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]]} |
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]]} |
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], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "q2"], "rhs" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "stored_d2"]]]} |
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]]} |
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]]} |
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]]} |
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], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "q3"], "rhs" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "stored_d3"]]]} |
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]]} |
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]]} |
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]]} |
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], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]]} |
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]]} |
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]} |
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, {
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"contexts" : [], "library" : ["ENTITY_DECLARATION", {
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"name" : ["IDENTIFIER", "d_latch"], "ports" : [{
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"names" : [["IDENTIFIER", "d"], ["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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, {
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"names" : [["IDENTIFIER", "q"]], "mode" : ["out"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
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]} |
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, {
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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"name" : ["IDENTIFIER", "basic"], "entity" : ["IDENTIFIER", "d_latch"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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"id" : ["IDENTIFIER", "latch_behavior"], "active_sigs" : [["SIMPLE_NAME", "clk"], ["SIMPLE_NAME", "d"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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"if_cases" : [{
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"if_cond" : ["EXPRESSION", {
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"id" : "=", "args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "clk"]]]} |
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]]} |
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]]} |
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], ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "'1'"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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"lhs" : ["SIMPLE_NAME", "q"], "rhs" : [{
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"value" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "d"]]]} |
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]]} |
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]]} |
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]]} |
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], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "2"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]]} |
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]} |
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]]} |
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]]} |
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]} |
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, {
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"contexts" : [], "library" : ["ENTITY_DECLARATION", {
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"name" : ["IDENTIFIER", "and2"], "ports" : [{
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"names" : [["IDENTIFIER", "a"], ["IDENTIFIER", "b"]], "mode" : ["in"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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, {
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"names" : [["IDENTIFIER", "y"]], "mode" : ["out"], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
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]} |
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, {
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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"name" : ["IDENTIFIER", "basic"], "entity" : ["IDENTIFIER", "and2"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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"id" : ["IDENTIFIER", "and2_behavior"], "active_sigs" : [["SIMPLE_NAME", "a"], ["SIMPLE_NAME", "b"]], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 285 |
"lhs" : ["SIMPLE_NAME", "y"], "rhs" : [{
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"value" : ["EXPRESSION", {
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| 287 |
"id" : "and", "args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "a"]]]} |
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]]} |
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]]} |
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]]} |
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], ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
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"args" : [["CALL", ["SIMPLE_NAME", "b"]]]} |
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]]} |
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| 301 |
]]} |
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]]} |
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]]} |
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| 304 |
], "delay" : ["EXPRESSION", {
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"args" : [["EXPRESSION", {
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| 306 |
"args" : [["EXPRESSION", {
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"args" : [["EXPRESSION", {
|
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| 308 |
"args" : [["CONSTANT_VALUE", {
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"value" : ["CST_LITERAL", "2"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]]} |
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]]} |
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]} |
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, {
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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"name" : ["IDENTIFIER", "struct"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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"declaration" : ["SIGNAL_DECLARATION", {
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"names" : [["IDENTIFIER", "int_clk"]], "typ" : {
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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| 326 |
]} |
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, {
|
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| 328 |
"declaration" : ["SIGNAL_DECLARATION", {
|
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"names" : [["IDENTIFIER", "mem"]], "typ" : {
|
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"name" : ["SIMPLE_NAME", "bit"]} |
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} |
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| 332 |
]} |
|
| 333 |
], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
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| 334 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{
|
|
| 335 |
"expr" : [{
|
|
| 336 |
"value" : ["EXPRESSION", {
|
|
| 337 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 338 |
"args" : [["EXPRESSION", {
|
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| 339 |
"args" : [["EXPRESSION", {
|
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| 340 |
"args" : [["EXPRESSION", {
|
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| 341 |
"args" : [["CALL", ["SIMPLE_NAME", "d0"]]]} |
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| 342 |
]]} |
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| 343 |
]]} |
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]]} |
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| 345 |
], ["EXPRESSION", {
|
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| 346 |
"args" : [["EXPRESSION", {
|
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| 347 |
"args" : [["EXPRESSION", {
|
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| 348 |
"args" : [["EXPRESSION", {
|
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| 349 |
"args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
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]]} |
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]]} |
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]]} |
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]]} |
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]} |
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]} |
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]} |
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| 357 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 358 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "mem"], "rhs" : [{
|
|
| 359 |
"expr" : [{
|
|
| 360 |
"value" : ["EXPRESSION", {
|
|
| 361 |
"args" : [["EXPRESSION", {
|
|
| 362 |
"args" : [["EXPRESSION", {
|
|
| 363 |
"args" : [["EXPRESSION", {
|
|
| 364 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
|
| 365 |
]]} |
|
| 366 |
]]} |
|
| 367 |
]]} |
|
| 368 |
]} |
|
| 369 |
]} |
|
| 370 |
]} |
|
| 371 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 372 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
|
|
| 373 |
"expr" : [{
|
|
| 374 |
"value" : ["EXPRESSION", {
|
|
| 375 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 376 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 377 |
"args" : [["EXPRESSION", {
|
|
| 378 |
"args" : [["EXPRESSION", {
|
|
| 379 |
"args" : [["EXPRESSION", {
|
|
| 380 |
"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
|
| 381 |
]]} |
|
| 382 |
]]} |
|
| 383 |
]]} |
|
| 384 |
], ["EXPRESSION", {
|
|
| 385 |
"args" : [["EXPRESSION", {
|
|
| 386 |
"args" : [["EXPRESSION", {
|
|
| 387 |
"args" : [["EXPRESSION", {
|
|
| 388 |
"args" : [["EXPRESSION", {
|
|
| 389 |
"args" : [["EXPRESSION", {
|
|
| 390 |
"args" : [["EXPRESSION", {
|
|
| 391 |
"args" : [["EXPRESSION", {
|
|
| 392 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
|
| 393 |
]]} |
|
| 394 |
]]} |
|
| 395 |
]]} |
|
| 396 |
]]} |
|
| 397 |
]]} |
|
| 398 |
]]} |
|
| 399 |
]]} |
|
| 400 |
]]} |
|
| 401 |
], ["EXPRESSION", {
|
|
| 402 |
"args" : [["EXPRESSION", {
|
|
| 403 |
"args" : [["EXPRESSION", {
|
|
| 404 |
"args" : [["EXPRESSION", {
|
|
| 405 |
"args" : [["CALL", ["SIMPLE_NAME", "d3"]]]} |
|
| 406 |
]]} |
|
| 407 |
]]} |
|
| 408 |
]]} |
|
| 409 |
]]} |
|
| 410 |
]} |
|
| 411 |
]} |
|
| 412 |
]} |
|
| 413 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 414 |
"name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
|
| 415 |
"actual_designator" : ["SIMPLE_NAME", "d0"]} |
|
| 416 |
, {
|
|
| 417 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]} |
|
| 418 |
, {
|
|
| 419 |
"actual_designator" : ["SIMPLE_NAME", "q0"]} |
|
| 420 |
]} |
|
| 421 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 422 |
"name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
|
| 423 |
"formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q1"]} |
|
| 424 |
, {
|
|
| 425 |
"formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "d1"]} |
|
| 426 |
, {
|
|
| 427 |
"formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "int_clk"]} |
|
| 428 |
]} |
|
| 429 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 430 |
"name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
|
| 431 |
"actual_designator" : ["SIMPLE_NAME", "d2"]} |
|
| 432 |
, {
|
|
| 433 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]} |
|
| 434 |
, {
|
|
| 435 |
"actual_designator" : ["SIMPLE_NAME", "q2"]} |
|
| 436 |
]} |
|
| 437 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 438 |
"name" : ["IDENTIFIER", "bit3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
|
| 439 |
"actual_designator" : ["SIMPLE_NAME", "d3"]} |
|
| 440 |
, {
|
|
| 441 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]} |
|
| 442 |
, {
|
|
| 443 |
"actual_designator" : ["SIMPLE_NAME", "q3"]} |
|
| 444 |
]} |
|
| 445 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 446 |
"name" : ["IDENTIFIER", "gate"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "and2"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
|
| 447 |
"actual_designator" : ["SIMPLE_NAME", "en"]} |
|
| 448 |
, {
|
|
| 449 |
"actual_designator" : ["SIMPLE_NAME", "clk"]} |
|
| 450 |
, {
|
|
| 451 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]} |
|
| 452 |
]} |
|
| 453 |
]]} |
|
| 454 |
]} |
|
| 455 |
]} |
|
| 456 |
} |
|
| vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate-memories.vhd | ||
|---|---|---|
| 1 |
--- Adapted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15 |
|
| 2 |
|
|
| 3 |
-- main entity |
|
| 4 |
entity reg4 is |
|
| 5 |
port (d0, d1, d2, d3, en, clk: in bit; |
|
| 6 |
q0, q1, q2, q3 : out bit ); |
|
| 7 |
end entity reg4; |
|
| 8 |
|
|
| 9 |
-- main archi |
|
| 10 |
architecture behav of reg4 is |
|
| 11 |
begin |
|
| 12 |
q1 <= '1'; |
|
| 13 |
storage: process (d0, d1, d2, d3, en, clk) is |
|
| 14 |
variable stored_d0, stored_d1, stored_d2, stored_d3: bit; |
|
| 15 |
begin |
|
| 16 |
if en = '1' and clk = '1' then |
|
| 17 |
stored_d0 := d0; |
|
| 18 |
stored_d1 := d1; |
|
| 19 |
stored_d2 := d2; |
|
| 20 |
stored_d3 := d3; |
|
| 21 |
end if; |
|
| 22 |
q0 <= stored_d0 after 5 ns; |
|
| 23 |
q1 <= stored_d1 after 5 ns; |
|
| 24 |
q2 <= stored_d2 after 5 ns; |
|
| 25 |
q3 <= stored_d3 after 5 ns; |
|
| 26 |
end process storage; |
|
| 27 |
end architecture behav; |
|
| 28 |
|
|
| 29 |
-- D-latch |
|
| 30 |
entity d_latch is |
|
| 31 |
port (d, clk: in bit; q: out bit); |
|
| 32 |
end entity d_latch; |
|
| 33 |
|
|
| 34 |
architecture basic of d_latch is |
|
| 35 |
begin |
|
| 36 |
latch_behavior : process (clk, d) is |
|
| 37 |
begin |
|
| 38 |
if clk = '1' then |
|
| 39 |
q <= d after 2 ns; |
|
| 40 |
end if; |
|
| 41 |
end process latch_behavior; |
|
| 42 |
end architecture basic; |
|
| 43 |
|
|
| 44 |
-- and-gate |
|
| 45 |
entity and2 is |
|
| 46 |
port (a, b: in bit; y: out bit); |
|
| 47 |
end entity and2; |
|
| 48 |
|
|
| 49 |
architecture basic of and2 is |
|
| 50 |
begin |
|
| 51 |
-- and2_behavior: process (a) is |
|
| 52 |
and2_behavior: process (a,b) is |
|
| 53 |
begin |
|
| 54 |
y <= a and b after 2 ns; |
|
| 55 |
end process and2_behavior; |
|
| 56 |
end architecture basic; |
|
| 57 |
|
|
| 58 |
-- Main archi |
|
| 59 |
architecture struct of reg4 is |
|
| 60 |
signal int_clk: bit; |
|
| 61 |
signal mem: bit; |
|
| 62 |
begin |
|
| 63 |
q0 <= d0 and mem; |
|
| 64 |
mem <= not d1; |
|
| 65 |
q1 <= d2 and (not mem) and d3; |
|
| 66 |
bit0: entity work.d_latch(basic) |
|
| 67 |
port map (d0, int_clk, q0); |
|
| 68 |
bit1: entity work.d_latch(basic) |
|
| 69 |
port map (q => q1, d => d1, clk => int_clk); |
|
| 70 |
bit2: entity work.d_latch(basic) |
|
| 71 |
port map (d2, int_clk, q2); |
|
| 72 |
bit3: entity work.d_latch(basic) |
|
| 73 |
port map (d3, int_clk, q3); |
|
| 74 |
gate: entity work.and2(basic) |
|
| 75 |
port map (en, clk, int_clk); |
|
| 76 |
end architecture struct; |
|
| vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.json | ||
|---|---|---|
| 14 | 14 |
]} |
| 15 | 15 |
, {
|
| 16 | 16 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
|
| 17 |
"name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
|
|
| 17 |
"name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 18 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
|
|
| 19 |
"expr" : [{
|
|
| 20 |
"value" : ["EXPRESSION", {
|
|
| 21 |
"args" : [["EXPRESSION", {
|
|
| 22 |
"args" : [["EXPRESSION", {
|
|
| 23 |
"args" : [["EXPRESSION", {
|
|
| 24 |
"args" : [["CONSTANT_VALUE", {
|
|
| 25 |
"value" : ["CST_LITERAL", "'1'"]} |
|
| 26 |
]]} |
|
| 27 |
]]} |
|
| 28 |
]]} |
|
| 29 |
]]} |
|
| 30 |
]} |
|
| 31 |
]} |
|
| 32 |
]} |
|
| 33 |
], ["PROCESS_STATEMENT", {
|
|
| 18 | 34 |
"id" : ["IDENTIFIER", "storage"], "PROCESS_DECLARATIVE_PART" : [{
|
| 19 | 35 |
"declaration" : ["VARIABLE_DECLARATION", {
|
| 20 | 36 |
"names" : [["IDENTIFIER", "stored_d0"], ["IDENTIFIER", "stored_d1"], ["IDENTIFIER", "stored_d2"], ["IDENTIFIER", "stored_d3"]], "typ" : {
|
| ... | ... | |
| 187 | 203 |
]]} |
| 188 | 204 |
]} |
| 189 | 205 |
]} |
| 190 |
], ["WAIT_STATEMENT"]]}
|
|
| 206 |
]]} |
|
| 191 | 207 |
]]} |
| 192 | 208 |
]} |
| 193 | 209 |
, {
|
| ... | ... | |
| 247 | 263 |
]} |
| 248 | 264 |
]]} |
| 249 | 265 |
]} |
| 250 |
], ["WAIT_STATEMENT"]]}
|
|
| 266 |
]]} |
|
| 251 | 267 |
]]} |
| 252 | 268 |
]} |
| 253 | 269 |
, {
|
| ... | ... | |
| 297 | 313 |
]]} |
| 298 | 314 |
]} |
| 299 | 315 |
]} |
| 300 |
], ["WAIT_STATEMENT"]]}
|
|
| 316 |
]]} |
|
| 301 | 317 |
]]} |
| 302 | 318 |
]} |
| 303 | 319 |
, {
|
| ... | ... | |
| 308 | 324 |
"name" : ["SIMPLE_NAME", "bit"]} |
| 309 | 325 |
} |
| 310 | 326 |
]} |
| 327 |
, {
|
|
| 328 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 329 |
"names" : [["IDENTIFIER", "mem"]], "typ" : {
|
|
| 330 |
"name" : ["SIMPLE_NAME", "bit"]} |
|
| 331 |
} |
|
| 332 |
]} |
|
| 311 | 333 |
], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
| 312 | 334 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{
|
| 313 | 335 |
"expr" : [{
|
| 314 | 336 |
"value" : ["EXPRESSION", {
|
| 315 |
"args" : [["EXPRESSION", {
|
|
| 337 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 316 | 338 |
"args" : [["EXPRESSION", {
|
| 317 | 339 |
"args" : [["EXPRESSION", {
|
| 318 |
"id" : "&", "args" : [["EXPRESSION", {
|
|
| 340 |
"args" : [["EXPRESSION", {
|
|
| 319 | 341 |
"args" : [["CALL", ["SIMPLE_NAME", "d0"]]]} |
| 320 |
], ["EXPRESSION", {
|
|
| 321 |
"args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
|
| 342 |
]]} |
|
| 343 |
]]} |
|
| 344 |
]]} |
|
| 345 |
], ["EXPRESSION", {
|
|
| 346 |
"args" : [["EXPRESSION", {
|
|
| 347 |
"args" : [["EXPRESSION", {
|
|
| 348 |
"args" : [["EXPRESSION", {
|
|
| 349 |
"args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
|
| 322 | 350 |
]]} |
| 323 | 351 |
]]} |
| 324 | 352 |
]]} |
| ... | ... | |
| 327 | 355 |
]} |
| 328 | 356 |
]} |
| 329 | 357 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
| 330 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
|
|
| 358 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "mem"], "rhs" : [{
|
|
| 331 | 359 |
"expr" : [{
|
| 332 | 360 |
"value" : ["EXPRESSION", {
|
| 333 | 361 |
"args" : [["EXPRESSION", {
|
| 334 | 362 |
"args" : [["EXPRESSION", {
|
| 335 | 363 |
"args" : [["EXPRESSION", {
|
| 336 |
"id" : "&", "args" : [["EXPRESSION", {
|
|
| 337 |
"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
|
| 338 |
], ["EXPRESSION", {
|
|
| 364 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "d1"]]]} |
|
| 365 |
]]} |
|
| 366 |
]]} |
|
| 367 |
]]} |
|
| 368 |
]} |
|
| 369 |
]} |
|
| 370 |
]} |
|
| 371 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 372 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
|
|
| 373 |
"expr" : [{
|
|
| 374 |
"value" : ["EXPRESSION", {
|
|
| 375 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 376 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 377 |
"args" : [["EXPRESSION", {
|
|
| 378 |
"args" : [["EXPRESSION", {
|
|
| 379 |
"args" : [["EXPRESSION", {
|
|
| 380 |
"args" : [["CALL", ["SIMPLE_NAME", "d2"]]]} |
|
| 381 |
]]} |
|
| 382 |
]]} |
|
| 383 |
]]} |
|
| 384 |
], ["EXPRESSION", {
|
|
| 385 |
"args" : [["EXPRESSION", {
|
|
| 386 |
"args" : [["EXPRESSION", {
|
|
| 387 |
"args" : [["EXPRESSION", {
|
|
| 388 |
"args" : [["EXPRESSION", {
|
|
| 389 |
"args" : [["EXPRESSION", {
|
|
| 390 |
"args" : [["EXPRESSION", {
|
|
| 391 |
"args" : [["EXPRESSION", {
|
|
| 392 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "mem"]]]} |
|
| 393 |
]]} |
|
| 394 |
]]} |
|
| 395 |
]]} |
|
| 396 |
]]} |
|
| 397 |
]]} |
|
| 398 |
]]} |
|
| 399 |
]]} |
|
| 400 |
]]} |
|
| 401 |
], ["EXPRESSION", {
|
|
| 402 |
"args" : [["EXPRESSION", {
|
|
| 403 |
"args" : [["EXPRESSION", {
|
|
| 404 |
"args" : [["EXPRESSION", {
|
|
| 339 | 405 |
"args" : [["CALL", ["SIMPLE_NAME", "d3"]]]} |
| 340 | 406 |
]]} |
| 341 | 407 |
]]} |
| ... | ... | |
| 354 | 420 |
]} |
| 355 | 421 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
| 356 | 422 |
"name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
| 357 |
"actual_designator" : ["SIMPLE_NAME", "d1"]}
|
|
| 423 |
"formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
|
|
| 358 | 424 |
, {
|
| 359 |
"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
|
|
| 425 |
"formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "d1"]}
|
|
| 360 | 426 |
, {
|
| 361 |
"actual_designator" : ["SIMPLE_NAME", "q1"]}
|
|
| 427 |
"formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
|
|
| 362 | 428 |
]} |
| 363 | 429 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
| 364 | 430 |
"name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
|
| vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd | ||
|---|---|---|
| 9 | 9 |
-- main archi |
| 10 | 10 |
architecture behav of reg4 is |
| 11 | 11 |
begin |
| 12 |
q1 <= '1'; |
|
| 12 | 13 |
storage: process (d0, d1, d2, d3, en, clk) is |
| 13 | 14 |
variable stored_d0, stored_d1, stored_d2, stored_d3: bit; |
| 14 | 15 |
begin |
| ... | ... | |
| 22 | 23 |
q1 <= stored_d1 after 5 ns; |
| 23 | 24 |
q2 <= stored_d2 after 5 ns; |
| 24 | 25 |
q3 <= stored_d3 after 5 ns; |
| 25 |
wait; |
|
| 26 | 26 |
end process storage; |
| 27 | 27 |
end architecture behav; |
| 28 | 28 |
|
| ... | ... | |
| 36 | 36 |
latch_behavior : process (clk, d) is |
| 37 | 37 |
begin |
| 38 | 38 |
if clk = '1' then |
| 39 |
q <= d after 2ns; |
|
| 39 |
q <= d after 2 ns;
|
|
| 40 | 40 |
end if; |
| 41 |
wait; |
|
| 42 | 41 |
end process latch_behavior; |
| 43 | 42 |
end architecture basic; |
| 44 | 43 |
|
| ... | ... | |
| 49 | 48 |
|
| 50 | 49 |
architecture basic of and2 is |
| 51 | 50 |
begin |
| 51 |
-- and2_behavior: process (a) is |
|
| 52 | 52 |
and2_behavior: process (a,b) is |
| 53 | 53 |
begin |
| 54 |
y <= a and b after 2ns; |
|
| 55 |
wait; |
|
| 54 |
y <= a and b after 2 ns; |
|
| 56 | 55 |
end process and2_behavior; |
| 57 | 56 |
end architecture basic; |
| 58 | 57 |
|
| 59 | 58 |
-- Main archi |
| 60 | 59 |
architecture struct of reg4 is |
| 61 | 60 |
signal int_clk: bit; |
| 61 |
signal mem: bit; |
|
| 62 | 62 |
begin |
| 63 |
q0 <= d0 & d1; |
|
| 64 |
q1 <= d2 & d3; |
|
| 63 |
q0 <= d0 and mem; |
|
| 64 |
mem <= not d1; |
|
| 65 |
q1 <= d2 and (not mem) and d3; |
|
| 65 | 66 |
bit0: entity work.d_latch(basic) |
| 66 | 67 |
port map (d0, int_clk, q0); |
| 67 | 68 |
bit1: entity work.d_latch(basic) |
| 68 |
port map (d1, int_clk, q1);
|
|
| 69 |
port map (q => q1, d => d1, clk => int_clk);
|
|
| 69 | 70 |
bit2: entity work.d_latch(basic) |
| 70 | 71 |
port map (d2, int_clk, q2); |
| 71 | 72 |
bit3: entity work.d_latch(basic) |
| vhdl_json/vhdl_files/2-exportOK/valencia/programmable_pulse_generator.json | ||
|---|---|---|
| 1 |
{
|
|
| 2 |
"DESIGN_FILE" : {
|
|
| 3 |
"design_units" : [{
|
|
| 4 |
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
|
|
| 5 |
"name" : ["IDENTIFIER", "ppg"], "ports" : [{
|
|
| 6 |
"names" : [["IDENTIFIER", "LoadDelay"]], "mode" : ["in"], "typ" : {
|
|
| 7 |
"name" : ["SIMPLE_NAME", "integer"]} |
|
| 8 |
} |
|
| 9 |
, {
|
|
| 10 |
"names" : [["IDENTIFIER", "LoadLength"]], "mode" : ["in"], "typ" : {
|
|
| 11 |
"name" : ["SIMPLE_NAME", "integer"]} |
|
| 12 |
} |
|
| 13 |
, {
|
|
| 14 |
"names" : [["IDENTIFIER", "Data"]], "mode" : ["in"], "typ" : {
|
|
| 15 |
"name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
|
|
| 16 |
"ranges" : [["RANGE_WITH_DIRECTION", {
|
|
| 17 |
"direction" : "to", "from" : ["EXPRESSION", {
|
|
| 18 |
"args" : [["EXPRESSION", {
|
|
| 19 |
"args" : [["CONSTANT_VALUE", {
|
|
| 20 |
"value" : ["CST_LITERAL", "0"]} |
|
| 21 |
]]} |
|
| 22 |
]]} |
|
| 23 |
], "_to" : ["EXPRESSION", {
|
|
| 24 |
"args" : [["EXPRESSION", {
|
|
| 25 |
"args" : [["CONSTANT_VALUE", {
|
|
| 26 |
"value" : ["CST_LITERAL", "7"]} |
|
| 27 |
]]} |
|
| 28 |
]]} |
|
| 29 |
]} |
|
| 30 |
]]} |
|
| 31 |
]} |
|
| 32 |
} |
|
| 33 |
, {
|
|
| 34 |
"names" : [["IDENTIFIER", "reset"]], "mode" : ["in"], "typ" : {
|
|
| 35 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
|
| 36 |
} |
|
| 37 |
, {
|
|
| 38 |
"names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
|
|
| 39 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
|
| 40 |
} |
|
| 41 |
, {
|
|
| 42 |
"names" : [["IDENTIFIER", "pulse"]], "mode" : ["out"], "typ" : {
|
|
| 43 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
|
| 44 |
} |
|
| 45 |
], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
|
| 46 |
]} |
|
| 47 |
, {
|
|
| 48 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
|
|
| 49 |
"name" : ["IDENTIFIER", "ppg1"], "entity" : ["IDENTIFIER", "ppg"], "ARCHITECTURE_DECLARATIVE_PART" : [{
|
|
| 50 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 51 |
"names" : [["IDENTIFIER", "out_pulse"]], "typ" : {
|
|
| 52 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
|
| 53 |
, "init_val" : ["EXPRESSION", {
|
|
| 54 |
"args" : [["EXPRESSION", {
|
|
| 55 |
"args" : [["EXPRESSION", {
|
|
| 56 |
"args" : [["EXPRESSION", {
|
|
| 57 |
"args" : [["CONSTANT_VALUE", {
|
|
| 58 |
"value" : ["CST_LITERAL", "'0'"]} |
|
| 59 |
]]} |
|
| 60 |
]]} |
|
| 61 |
]]} |
|
| 62 |
]]} |
|
| 63 |
]} |
|
| 64 |
]} |
|
| 65 |
, {
|
|
| 66 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 67 |
"names" : [["IDENTIFIER", "in_delay"]], "typ" : {
|
|
| 68 |
"name" : ["SIMPLE_NAME", "integer"]} |
|
| 69 |
, "init_val" : ["EXPRESSION", {
|
|
| 70 |
"args" : [["EXPRESSION", {
|
|
| 71 |
"args" : [["EXPRESSION", {
|
|
| 72 |
"args" : [["EXPRESSION", {
|
|
| 73 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadDelay"]]]} |
|
| 74 |
]]} |
|
| 75 |
]]} |
|
| 76 |
]]} |
|
| 77 |
]} |
|
| 78 |
]} |
|
| 79 |
, {
|
|
| 80 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 81 |
"names" : [["IDENTIFIER", "in_length"]], "typ" : {
|
|
| 82 |
"name" : ["SIMPLE_NAME", "integer"]} |
|
| 83 |
, "init_val" : ["EXPRESSION", {
|
|
| 84 |
"args" : [["EXPRESSION", {
|
|
| 85 |
"args" : [["EXPRESSION", {
|
|
| 86 |
"args" : [["EXPRESSION", {
|
|
| 87 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadLength"]]]} |
|
| 88 |
]]} |
|
| 89 |
]]} |
|
| 90 |
]]} |
|
| 91 |
]} |
|
| 92 |
]} |
|
| 93 |
], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
|
|
| 94 |
"id" : ["IDENTIFIER", "p"], "active_sigs" : [["SIMPLE_NAME", "reset"], ["SIMPLE_NAME", "clk"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
|
|
| 95 |
"if_cases" : [{
|
|
| 96 |
"if_cond" : ["EXPRESSION", {
|
|
| 97 |
"args" : [["EXPRESSION", {
|
|
| 98 |
"args" : [["EXPRESSION", {
|
|
| 99 |
"args" : [["EXPRESSION", {
|
|
| 100 |
"args" : [["EXPRESSION", {
|
|
| 101 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 102 |
"args" : [["EXPRESSION", {
|
|
| 103 |
"args" : [["EXPRESSION", {
|
|
| 104 |
"args" : [["EXPRESSION", {
|
|
| 105 |
"args" : [["CALL", ["ATTRIBUTE_NAME", {
|
|
| 106 |
"id" : ["SIMPLE_NAME", "clk"], "designator" : ["SIMPLE_NAME", "event"]} |
|
| 107 |
]]]} |
|
| 108 |
]]} |
|
| 109 |
]]} |
|
| 110 |
]]} |
|
| 111 |
], ["EXPRESSION", {
|
|
| 112 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 113 |
"args" : [["EXPRESSION", {
|
|
| 114 |
"args" : [["EXPRESSION", {
|
|
| 115 |
"args" : [["CALL", ["SIMPLE_NAME", "clk"]]]} |
|
| 116 |
]]} |
|
| 117 |
]]} |
|
| 118 |
], ["EXPRESSION", {
|
|
| 119 |
"args" : [["EXPRESSION", {
|
|
| 120 |
"args" : [["EXPRESSION", {
|
|
| 121 |
"args" : [["CONSTANT_VALUE", {
|
|
| 122 |
"value" : ["CST_LITERAL", "'1'"]} |
|
| 123 |
]]} |
|
| 124 |
]]} |
|
| 125 |
]]} |
|
| 126 |
]]} |
|
| 127 |
]]} |
|
| 128 |
]]} |
|
| 129 |
]]} |
|
| 130 |
]]} |
|
| 131 |
]]} |
|
| 132 |
], "if_block" : [["IF_STATEMENT", {
|
|
| 133 |
"if_cases" : [{
|
|
| 134 |
"if_cond" : ["EXPRESSION", {
|
|
| 135 |
"args" : [["EXPRESSION", {
|
|
| 136 |
"args" : [["EXPRESSION", {
|
|
| 137 |
"args" : [["EXPRESSION", {
|
|
| 138 |
"args" : [["EXPRESSION", {
|
|
| 139 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 140 |
"args" : [["EXPRESSION", {
|
|
| 141 |
"args" : [["EXPRESSION", {
|
|
| 142 |
"args" : [["CALL", ["SIMPLE_NAME", "reset"]]]} |
|
| 143 |
]]} |
|
| 144 |
]]} |
|
| 145 |
], ["EXPRESSION", {
|
|
| 146 |
"args" : [["EXPRESSION", {
|
|
| 147 |
"args" : [["EXPRESSION", {
|
|
| 148 |
"args" : [["CONSTANT_VALUE", {
|
|
| 149 |
"value" : ["CST_LITERAL", "'1'"]} |
|
| 150 |
]]} |
|
| 151 |
]]} |
|
| 152 |
]]} |
|
| 153 |
]]} |
|
| 154 |
]]} |
|
| 155 |
]]} |
|
| 156 |
]]} |
|
| 157 |
]]} |
|
| 158 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 159 |
"lhs" : ["SIMPLE_NAME", "out_pulse"], "rhs" : [{
|
|
| 160 |
"value" : ["EXPRESSION", {
|
|
| 161 |
"args" : [["EXPRESSION", {
|
|
| 162 |
"args" : [["EXPRESSION", {
|
|
| 163 |
"args" : [["EXPRESSION", {
|
|
| 164 |
"args" : [["CONSTANT_VALUE", {
|
|
| 165 |
"value" : ["CST_LITERAL", "'0'"]} |
|
| 166 |
]]} |
|
| 167 |
]]} |
|
| 168 |
]]} |
|
| 169 |
]]} |
|
| 170 |
]} |
|
| 171 |
]} |
|
| 172 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 173 |
"lhs" : ["SIMPLE_NAME", "in_delay"], "rhs" : [{
|
|
| 174 |
"value" : ["EXPRESSION", {
|
|
| 175 |
"args" : [["EXPRESSION", {
|
|
| 176 |
"args" : [["EXPRESSION", {
|
|
| 177 |
"args" : [["EXPRESSION", {
|
|
| 178 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadDelay"]]]} |
|
| 179 |
]]} |
|
| 180 |
]]} |
|
| 181 |
]]} |
|
| 182 |
]} |
|
| 183 |
]} |
|
| 184 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 185 |
"lhs" : ["SIMPLE_NAME", "in_length"], "rhs" : [{
|
|
| 186 |
"value" : ["EXPRESSION", {
|
|
| 187 |
"args" : [["EXPRESSION", {
|
|
| 188 |
"args" : [["EXPRESSION", {
|
|
| 189 |
"args" : [["EXPRESSION", {
|
|
| 190 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadLength"]]]} |
|
| 191 |
]]} |
|
| 192 |
]]} |
|
| 193 |
]]} |
|
| 194 |
]} |
|
| 195 |
]} |
|
| 196 |
]]} |
|
| 197 |
], "default" : [["IF_STATEMENT", {
|
|
| 198 |
"if_cases" : [{
|
|
| 199 |
"if_cond" : ["EXPRESSION", {
|
|
| 200 |
"args" : [["EXPRESSION", {
|
|
| 201 |
"args" : [["EXPRESSION", {
|
|
| 202 |
"args" : [["EXPRESSION", {
|
|
| 203 |
"args" : [["EXPRESSION", {
|
|
| 204 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 205 |
"args" : [["EXPRESSION", {
|
|
| 206 |
"args" : [["EXPRESSION", {
|
|
| 207 |
"args" : [["CALL", ["SIMPLE_NAME", "in_delay"]]]} |
|
| 208 |
]]} |
|
| 209 |
]]} |
|
| 210 |
], ["EXPRESSION", {
|
|
| 211 |
"args" : [["EXPRESSION", {
|
|
| 212 |
"args" : [["EXPRESSION", {
|
|
| 213 |
"args" : [["CONSTANT_VALUE", {
|
|
| 214 |
"value" : ["CST_LITERAL", "0"]} |
|
| 215 |
]]} |
|
| 216 |
]]} |
|
| 217 |
]]} |
|
| 218 |
]]} |
|
| 219 |
]]} |
|
| 220 |
]]} |
|
| 221 |
]]} |
|
| 222 |
]]} |
|
| 223 |
], "if_block" : [["IF_STATEMENT", {
|
|
| 224 |
"if_cases" : [{
|
|
| 225 |
"if_cond" : ["EXPRESSION", {
|
|
| 226 |
"args" : [["EXPRESSION", {
|
|
| 227 |
"args" : [["EXPRESSION", {
|
|
| 228 |
"args" : [["EXPRESSION", {
|
|
| 229 |
"args" : [["EXPRESSION", {
|
|
| 230 |
"id" : ">", "args" : [["EXPRESSION", {
|
|
| 231 |
"args" : [["EXPRESSION", {
|
|
| 232 |
"args" : [["EXPRESSION", {
|
|
| 233 |
"args" : [["CALL", ["SIMPLE_NAME", "in_length"]]]} |
|
| 234 |
]]} |
|
| 235 |
]]} |
|
| 236 |
], ["EXPRESSION", {
|
|
| 237 |
"args" : [["EXPRESSION", {
|
|
| 238 |
"args" : [["EXPRESSION", {
|
|
| 239 |
"args" : [["CONSTANT_VALUE", {
|
|
| 240 |
"value" : ["CST_LITERAL", "0"]} |
|
| 241 |
]]} |
|
| 242 |
]]} |
|
| 243 |
]]} |
|
| 244 |
]]} |
|
| 245 |
]]} |
|
| 246 |
]]} |
|
| 247 |
]]} |
|
| 248 |
]]} |
|
| 249 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 250 |
"lhs" : ["SIMPLE_NAME", "in_length"], "rhs" : [{
|
|
| 251 |
"value" : ["EXPRESSION", {
|
|
| 252 |
"args" : [["EXPRESSION", {
|
|
| 253 |
"args" : [["EXPRESSION", {
|
|
| 254 |
"args" : [["EXPRESSION", {
|
|
| 255 |
"id" : "-", "args" : [["EXPRESSION", {
|
|
| 256 |
"args" : [["CALL", ["SIMPLE_NAME", "in_length"]]]} |
|
| 257 |
], ["EXPRESSION", {
|
|
| 258 |
"args" : [["CONSTANT_VALUE", {
|
|
| 259 |
"value" : ["CST_LITERAL", "1"]} |
|
| 260 |
]]} |
|
| 261 |
]]} |
|
| 262 |
]]} |
|
| 263 |
]]} |
|
| 264 |
]]} |
|
| 265 |
]} |
|
| 266 |
]} |
|
| 267 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 268 |
"lhs" : ["SIMPLE_NAME", "out_pulse"], "rhs" : [{
|
|
| 269 |
"value" : ["EXPRESSION", {
|
|
| 270 |
"args" : [["EXPRESSION", {
|
|
| 271 |
"args" : [["EXPRESSION", {
|
|
| 272 |
"args" : [["EXPRESSION", {
|
|
| 273 |
"args" : [["CONSTANT_VALUE", {
|
|
| 274 |
"value" : ["CST_LITERAL", "'1'"]} |
|
| 275 |
]]} |
|
| 276 |
]]} |
|
| 277 |
]]} |
|
| 278 |
]]} |
|
| 279 |
]} |
|
| 280 |
]} |
|
| 281 |
]]} |
|
| 282 |
], "default" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 283 |
"lhs" : ["SIMPLE_NAME", "in_length"], "rhs" : [{
|
|
| 284 |
"value" : ["EXPRESSION", {
|
|
| 285 |
"args" : [["EXPRESSION", {
|
|
| 286 |
"args" : [["EXPRESSION", {
|
|
| 287 |
"args" : [["EXPRESSION", {
|
|
| 288 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadLength"]]]} |
|
| 289 |
]]} |
|
| 290 |
]]} |
|
| 291 |
]]} |
|
| 292 |
]} |
|
| 293 |
]} |
|
| 294 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 295 |
"lhs" : ["SIMPLE_NAME", "in_delay"], "rhs" : [{
|
|
| 296 |
"value" : ["EXPRESSION", {
|
|
| 297 |
"args" : [["EXPRESSION", {
|
|
| 298 |
"args" : [["EXPRESSION", {
|
|
| 299 |
"args" : [["EXPRESSION", {
|
|
| 300 |
"args" : [["CALL", ["SIMPLE_NAME", "LoadDelay"]]]} |
|
| 301 |
]]} |
|
| 302 |
]]} |
|
| 303 |
]]} |
|
| 304 |
]} |
|
| 305 |
]} |
|
| 306 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 307 |
"lhs" : ["SIMPLE_NAME", "out_pulse"], "rhs" : [{
|
|
| 308 |
"value" : ["EXPRESSION", {
|
|
| 309 |
"args" : [["EXPRESSION", {
|
|
| 310 |
"args" : [["EXPRESSION", {
|
|
| 311 |
"args" : [["EXPRESSION", {
|
|
| 312 |
"args" : [["CONSTANT_VALUE", {
|
|
| 313 |
"value" : ["CST_LITERAL", "'0'"]} |
|
| 314 |
]]} |
|
| 315 |
]]} |
|
| 316 |
]]} |
|
| 317 |
]]} |
|
| 318 |
]} |
|
| 319 |
]} |
|
| 320 |
]]} |
|
| 321 |
]]} |
|
| 322 |
], "default" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 323 |
"lhs" : ["SIMPLE_NAME", "in_delay"], "rhs" : [{
|
|
| 324 |
"value" : ["EXPRESSION", {
|
|
| 325 |
"args" : [["EXPRESSION", {
|
|
| 326 |
"args" : [["EXPRESSION", {
|
|
| 327 |
"args" : [["EXPRESSION", {
|
|
| 328 |
"id" : "-", "args" : [["EXPRESSION", {
|
|
| 329 |
"args" : [["CALL", ["SIMPLE_NAME", "in_delay"]]]} |
|
| 330 |
], ["EXPRESSION", {
|
|
| 331 |
"args" : [["CONSTANT_VALUE", {
|
|
| 332 |
"value" : ["CST_LITERAL", "1"]} |
|
| 333 |
]]} |
|
| 334 |
]]} |
|
| 335 |
]]} |
|
| 336 |
]]} |
|
| 337 |
]]} |
|
| 338 |
]} |
|
| 339 |
]} |
|
| 340 |
]]} |
|
| 341 |
]]} |
|
| 342 |
]]} |
|
| 343 |
]} |
|
| 344 |
]]} |
|
| 345 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 346 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "pulse"], "rhs" : [{
|
|
| 347 |
"expr" : [{
|
|
| 348 |
"value" : ["EXPRESSION", {
|
|
| 349 |
"args" : [["EXPRESSION", {
|
|
| 350 |
"args" : [["EXPRESSION", {
|
|
| 351 |
"args" : [["EXPRESSION", {
|
|
| 352 |
"args" : [["CALL", ["SIMPLE_NAME", "out_pulse"]]]} |
|
| 353 |
]]} |
|
| 354 |
]]} |
|
| 355 |
]]} |
|
| 356 |
]} |
|
| 357 |
]} |
|
| 358 |
]} |
|
| 359 |
]]} |
|
| 360 |
]} |
|
| 361 |
]} |
|
| 362 |
} |
|
| vhdl_json/vhdl_files/2-exportOK/valencia/programmable_pulse_generator.vhd | ||
|---|---|---|
| 1 |
library ieee; |
|
| 2 |
use ieee.std_logic_1164.all; |
|
| 3 |
|
|
| 4 |
entity ppg is |
|
| 5 |
port ( |
|
| 6 |
LoadDelay : in integer; |
|
| 7 |
LoadLength : in integer; |
|
| 8 |
Data : in std_logic_vector (0 to 7); |
|
| 9 |
reset : in std_logic; |
|
| 10 |
clk : in std_logic; |
|
| 11 |
pulse : out std_logic |
|
| 12 |
); |
|
| 13 |
end ppg; |
|
| 14 |
|
|
| 15 |
architecture ppg1 of ppg is |
|
| 16 |
signal out_pulse : std_logic := '0'; |
|
| 17 |
signal in_delay : integer := LoadDelay; |
|
| 18 |
signal in_length : integer := LoadLength; |
|
| 19 |
begin |
|
| 20 |
p : process (reset, clk) |
|
| 21 |
begin |
|
| 22 |
if (clk'event and clk = '1') |
|
| 23 |
then |
|
| 24 |
if (reset = '1') |
|
| 25 |
then |
|
| 26 |
out_pulse <= '0'; |
|
| 27 |
in_delay <= LoadDelay; |
|
| 28 |
in_length <= LoadLength; |
|
| 29 |
else |
|
| 30 |
if (in_delay = 0) |
|
| 31 |
then |
|
| 32 |
if (in_length > 0) |
|
| 33 |
then |
|
| 34 |
in_length <= in_length - 1; |
|
| 35 |
out_pulse <= '1'; |
|
| 36 |
else |
|
| 37 |
in_length <= LoadLength; |
|
| 38 |
in_delay <= LoadDelay; |
|
| 39 |
out_pulse <= '0'; |
|
| 40 |
end if; |
|
| 41 |
else |
|
| 42 |
in_delay <= in_delay - 1; |
|
| 43 |
end if; |
|
| 44 |
end if; |
|
| 45 |
end if; |
|
| 46 |
end process p; |
|
| 47 |
|
|
| 48 |
pulse <= out_pulse; |
|
| 49 |
end ppg1; |
|
| vhdl_json/vhdl_files/2-exportOK/valencia/two_counters.json | ||
|---|---|---|
| 1 |
{
|
|
| 2 |
"DESIGN_FILE" : {
|
|
| 3 |
"design_units" : [{
|
|
| 4 |
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
|
|
| 5 |
"name" : ["IDENTIFIER", "counter"], "ports" : [{
|
|
| 6 |
"names" : [["IDENTIFIER", "x"]], "mode" : ["in"], "typ" : {
|
|
| 7 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 8 |
} |
|
| 9 |
, {
|
|
| 10 |
"names" : [["IDENTIFIER", "o"]], "mode" : ["out"], "typ" : {
|
|
| 11 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 12 |
} |
|
| 13 |
], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
|
| 14 |
]} |
|
| 15 |
, {
|
|
| 16 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
|
|
| 17 |
"name" : ["IDENTIFIER", "greycounter"], "entity" : ["IDENTIFIER", "counter"], "ARCHITECTURE_DECLARATIVE_PART" : [{
|
|
| 18 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 19 |
"names" : [["IDENTIFIER", "a"], ["IDENTIFIER", "b"]], "typ" : {
|
|
| 20 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 21 |
, "init_val" : ["EXPRESSION", {
|
|
| 22 |
"args" : [["EXPRESSION", {
|
|
| 23 |
"args" : [["EXPRESSION", {
|
|
| 24 |
"args" : [["EXPRESSION", {
|
|
| 25 |
"args" : [["CALL", ["SIMPLE_NAME", "false"]]]} |
|
| 26 |
]]} |
|
| 27 |
]]} |
|
| 28 |
]]} |
|
| 29 |
]} |
|
| 30 |
]} |
|
| 31 |
], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 32 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "a"], "rhs" : [{
|
|
| 33 |
"expr" : [{
|
|
| 34 |
"value" : ["EXPRESSION", {
|
|
| 35 |
"args" : [["EXPRESSION", {
|
|
| 36 |
"args" : [["EXPRESSION", {
|
|
| 37 |
"args" : [["EXPRESSION", {
|
|
| 38 |
"args" : [["CALL", ["SIMPLE_NAME", "b"]]]} |
|
| 39 |
]]} |
|
| 40 |
]]} |
|
| 41 |
]]} |
|
| 42 |
]} |
|
| 43 |
]} |
|
| 44 |
]} |
|
| 45 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 46 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "b"], "rhs" : [{
|
|
| 47 |
"expr" : [{
|
|
| 48 |
"value" : ["EXPRESSION", {
|
|
| 49 |
"args" : [["EXPRESSION", {
|
|
| 50 |
"args" : [["EXPRESSION", {
|
|
| 51 |
"args" : [["EXPRESSION", {
|
|
| 52 |
"args" : [["CALL", ["SIMPLE_NAME", "a"]]]} |
|
| 53 |
]]} |
|
| 54 |
]]} |
|
| 55 |
]]} |
|
| 56 |
]} |
|
| 57 |
]} |
|
| 58 |
]} |
|
| 59 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 60 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "o"], "rhs" : [{
|
|
| 61 |
"expr" : [{
|
|
| 62 |
"value" : ["EXPRESSION", {
|
|
| 63 |
"id" : "and", "args" : [["EXPRESSION", {
|
|
| 64 |
"args" : [["EXPRESSION", {
|
|
| 65 |
"args" : [["EXPRESSION", {
|
|
| 66 |
"args" : [["EXPRESSION", {
|
|
| 67 |
"args" : [["CALL", ["SIMPLE_NAME", "a"]]]} |
|
| 68 |
]]} |
|
| 69 |
]]} |
|
| 70 |
]]} |
|
| 71 |
], ["EXPRESSION", {
|
|
| 72 |
"args" : [["EXPRESSION", {
|
|
| 73 |
"args" : [["EXPRESSION", {
|
|
| 74 |
"args" : [["EXPRESSION", {
|
|
| 75 |
"args" : [["CALL", ["SIMPLE_NAME", "b"]]]} |
|
| 76 |
]]} |
|
| 77 |
]]} |
|
| 78 |
]]} |
|
| 79 |
]]} |
|
| 80 |
]} |
|
| 81 |
]} |
|
| 82 |
]} |
|
| 83 |
]]} |
|
| 84 |
]} |
|
| 85 |
, {
|
|
| 86 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
|
|
| 87 |
"name" : ["IDENTIFIER", "intloopcounter"], "entity" : ["IDENTIFIER", "counter"], "ARCHITECTURE_DECLARATIVE_PART" : [{
|
|
| 88 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 89 |
"names" : [["IDENTIFIER", "t"]], "typ" : {
|
|
| 90 |
"name" : ["SIMPLE_NAME", "integer"]} |
|
| 91 |
, "init_val" : ["EXPRESSION", {
|
|
| 92 |
"args" : [["EXPRESSION", {
|
|
| 93 |
"args" : [["EXPRESSION", {
|
|
| 94 |
"args" : [["EXPRESSION", {
|
|
| 95 |
"args" : [["CONSTANT_VALUE", {
|
|
| 96 |
"value" : ["CST_LITERAL", "0"]} |
|
| 97 |
]]} |
|
| 98 |
]]} |
|
| 99 |
]]} |
|
| 100 |
]]} |
|
| 101 |
]} |
|
| 102 |
]} |
|
| 103 |
], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
|
|
| 104 |
"id" : ["IDENTIFIER", "p"], "active_sigs" : [["SIMPLE_NAME", "t"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
|
|
| 105 |
"if_cases" : [{
|
|
| 106 |
"if_cond" : ["EXPRESSION", {
|
|
| 107 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 108 |
"args" : [["EXPRESSION", {
|
|
| 109 |
"args" : [["EXPRESSION", {
|
|
| 110 |
"args" : [["CALL", ["SIMPLE_NAME", "t"]]]} |
|
| 111 |
]]} |
|
| 112 |
]]} |
|
| 113 |
], ["EXPRESSION", {
|
|
| 114 |
"args" : [["EXPRESSION", {
|
|
| 115 |
"args" : [["EXPRESSION", {
|
|
| 116 |
"args" : [["CONSTANT_VALUE", {
|
|
| 117 |
"value" : ["CST_LITERAL", "3"]} |
|
| 118 |
]]} |
|
| 119 |
]]} |
|
| 120 |
]]} |
|
| 121 |
]]} |
|
| 122 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 123 |
"lhs" : ["SIMPLE_NAME", "t"], "rhs" : [{
|
|
| 124 |
"value" : ["EXPRESSION", {
|
|
| 125 |
"args" : [["EXPRESSION", {
|
|
| 126 |
"args" : [["EXPRESSION", {
|
|
| 127 |
"args" : [["EXPRESSION", {
|
|
| 128 |
"args" : [["CONSTANT_VALUE", {
|
|
| 129 |
"value" : ["CST_LITERAL", "0"]} |
|
| 130 |
]]} |
|
| 131 |
]]} |
|
| 132 |
]]} |
|
| 133 |
]]} |
|
| 134 |
]} |
|
| 135 |
]} |
|
| 136 |
]]} |
|
| 137 |
], "default" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
|
|
| 138 |
"lhs" : ["SIMPLE_NAME", "t"], "rhs" : [{
|
|
| 139 |
"value" : ["EXPRESSION", {
|
|
| 140 |
"args" : [["EXPRESSION", {
|
|
| 141 |
"args" : [["EXPRESSION", {
|
|
| 142 |
"args" : [["EXPRESSION", {
|
|
| 143 |
"id" : "+", "args" : [["EXPRESSION", {
|
|
| 144 |
"args" : [["CALL", ["SIMPLE_NAME", "t"]]]} |
|
| 145 |
], ["EXPRESSION", {
|
|
| 146 |
"args" : [["CONSTANT_VALUE", {
|
|
| 147 |
"value" : ["CST_LITERAL", "1"]} |
|
| 148 |
]]} |
|
| 149 |
]]} |
|
| 150 |
]]} |
|
| 151 |
]]} |
|
| 152 |
]]} |
|
| 153 |
]} |
|
| 154 |
]} |
|
| 155 |
]]} |
|
| 156 |
]]} |
|
| 157 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 158 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "o"], "rhs" : [{
|
|
| 159 |
"expr" : [{
|
|
| 160 |
"value" : ["EXPRESSION", {
|
|
| 161 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 162 |
"args" : [["EXPRESSION", {
|
|
| 163 |
"args" : [["EXPRESSION", {
|
|
| 164 |
"args" : [["CALL", ["SIMPLE_NAME", "t"]]]} |
|
| 165 |
]]} |
|
| 166 |
]]} |
|
| 167 |
], ["EXPRESSION", {
|
|
| 168 |
"args" : [["EXPRESSION", {
|
|
| 169 |
"args" : [["EXPRESSION", {
|
|
| 170 |
"args" : [["CONSTANT_VALUE", {
|
|
| 171 |
"value" : ["CST_LITERAL", "2"]} |
|
| 172 |
]]} |
|
| 173 |
]]} |
|
| 174 |
]]} |
|
| 175 |
]]} |
|
| 176 |
]} |
|
| 177 |
]} |
|
| 178 |
]} |
|
| 179 |
]]} |
|
| 180 |
]} |
|
| 181 |
, {
|
|
| 182 |
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
|
|
| 183 |
"name" : ["IDENTIFIER", "top"], "ports" : [{
|
|
| 184 |
"names" : [["IDENTIFIER", "x"]], "mode" : ["in"], "typ" : {
|
|
| 185 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 186 |
} |
|
| 187 |
, {
|
|
| 188 |
"names" : [["IDENTIFIER", "ok"]], "mode" : ["out"], "typ" : {
|
|
| 189 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 190 |
} |
|
| 191 |
], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
|
| 192 |
]} |
|
| 193 |
, {
|
|
| 194 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
|
|
| 195 |
"name" : ["IDENTIFIER", "top_most"], "entity" : ["IDENTIFIER", "top"], "ARCHITECTURE_DECLARATIVE_PART" : [{
|
|
| 196 |
"declaration" : ["SIGNAL_DECLARATION", {
|
|
| 197 |
"names" : [["IDENTIFIER", "b"], ["IDENTIFIER", "d"]], "typ" : {
|
|
| 198 |
"name" : ["SIMPLE_NAME", "boolean"]} |
|
| 199 |
} |
|
| 200 |
]} |
|
| 201 |
], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 202 |
"name" : ["IDENTIFIER", "gc"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "counter"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "greycounter"], "port_map" : [{
|
|
| 203 |
"actual_designator" : ["SIMPLE_NAME", "x"]} |
|
| 204 |
, {
|
|
| 205 |
"actual_designator" : ["SIMPLE_NAME", "b"]} |
|
| 206 |
]} |
|
| 207 |
], ["COMPONENT_INSTANTIATION_STATEMENT", {
|
|
| 208 |
"name" : ["IDENTIFIER", "ilc"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "counter"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "intloopcounter"], "port_map" : [{
|
|
| 209 |
"actual_designator" : ["SIMPLE_NAME", "x"]} |
|
| 210 |
, {
|
|
| 211 |
"actual_designator" : ["SIMPLE_NAME", "d"]} |
|
| 212 |
]} |
|
| 213 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
|
| 214 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "ok"], "rhs" : [{
|
|
| 215 |
"expr" : [{
|
|
| 216 |
"value" : ["EXPRESSION", {
|
|
| 217 |
"id" : "=", "args" : [["EXPRESSION", {
|
|
| 218 |
"args" : [["EXPRESSION", {
|
|
| 219 |
"args" : [["EXPRESSION", {
|
|
| 220 |
"args" : [["CALL", ["SIMPLE_NAME", "b"]]]} |
|
| 221 |
]]} |
|
| 222 |
]]} |
|
| 223 |
], ["EXPRESSION", {
|
|
| 224 |
"args" : [["EXPRESSION", {
|
|
| 225 |
"args" : [["EXPRESSION", {
|
|
| 226 |
"args" : [["CALL", ["SIMPLE_NAME", "d"]]]} |
|
| 227 |
]]} |
|
| 228 |
]]} |
|
| 229 |
]]} |
|
| 230 |
]} |
|
| 231 |
]} |
|
| 232 |
]} |
|
| 233 |
]]} |
|
| 234 |
]} |
|
| 235 |
]} |
|
| 236 |
} |
|
| vhdl_json/vhdl_files/2-exportOK/valencia/two_counters.vhd | ||
|---|---|---|
| 1 |
library ieee; |
|
| 2 |
use ieee.std_logic_1164.all; |
|
| 3 |
|
|
| 4 |
entity counter is |
|
| 5 |
port (x: in boolean; |
|
| 6 |
o: out boolean); |
|
| 7 |
end counter; |
|
| 8 |
|
|
| 9 |
architecture greycounter of counter is |
|
| 10 |
signal a,b: boolean := false; |
|
| 11 |
begin |
|
| 12 |
a <= b; |
|
| 13 |
b <= a; |
|
| 14 |
o <= a and b; |
|
| 15 |
end; |
|
| 16 |
|
|
| 17 |
architecture intloopcounter of counter is |
|
| 18 |
signal t: integer := 0; |
|
| 19 |
begin |
|
| 20 |
p : process (t) |
|
| 21 |
begin |
|
| 22 |
if t = 3 |
|
| 23 |
then |
|
| 24 |
t <= 0; |
|
| 25 |
else |
|
| 26 |
t <= t + 1; |
|
| 27 |
end if; |
|
| 28 |
end process p; |
|
| 29 |
o <= t = 2; |
|
| 30 |
end; |
|
| 31 |
|
|
| 32 |
library ieee; |
|
| 33 |
use ieee.std_logic_1164.all; |
|
| 34 |
|
|
| 35 |
entity top is |
|
| 36 |
port (x : in boolean; |
|
| 37 |
ok: out boolean); |
|
| 38 |
end top; |
|
| 39 |
|
|
| 40 |
-- Ensures ok; |
|
| 41 |
architecture top_most of top is |
|
| 42 |
signal b,d: boolean; |
|
| 43 |
begin |
|
| 44 |
gc: entity work.counter(greycounter) |
|
| 45 |
port map (x,b); |
|
| 46 |
ilc: entity work.counter(intloopcounter) |
|
| 47 |
port map (x,d); |
|
| 48 |
ok <= b = d; |
|
| 49 |
end; |
|
Also available in: Unified diff