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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1761.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1761.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s05b01x00p21n01i01761ent IS
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END c09s05b01x00p21n01i01761ent;
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ARCHITECTURE c09s05b01x00p21n01i01761arch OF c09s05b01x00p21n01i01761ent IS
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  signal TS1,TS2   : integer;
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  signal B,C   : integer;
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  signal D,E,F   : bit;
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BEGIN
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  TS1 <= transport 1 after 10 ns when B = C else
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         2 after 10 ns when B > C else
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         3 after 10 ns;
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  TS2 <= transport 4-1 after 10 ns when D = '1' else
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         5+1 after 10 ns when E = '1' else
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         6*2 after 10 ns when F = '1' else
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         8/2 after 10 ns;
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  TESTING: PROCESS(TS1,TS2)
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  BEGIN
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    if ( now > 1 ns) then
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      assert NOT(TS1=1 and TS2=4) 
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        report "***PASSED TEST: c09s05b01x00p21n01i01761" 
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        severity NOTE;
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      assert (TS1=1 and TS2=4) 
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        report "***FAILED TEST: c09s05b01x00p21n01i01761 - Conditions in the conditional signal assignment statement should be valid." 
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        severity ERROR;
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    end if;
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  END PROCESS TESTING;
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END c09s05b01x00p21n01i01761arch;