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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1756.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s05b01x00p01n01i01756ent IS
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END c09s05b01x00p01n01i01756ent;
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ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
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  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
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  signal count : integer ;
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  signal ECLK  : t_wlogic;
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  signal ECLK2 : t_wlogic;
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  signal ECL   : integer := 1;
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BEGIN
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  count <=    0 after  0 ns,
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              1 after 10 ns,
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              2 after 20 ns,
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              3 after 30 ns,
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              4 after 40 ns,
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              5 after 50 ns,
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              6 after 60 ns;
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  ----------------------------------------------------------------------
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  ECLK <=  U   after 1 ns WHEN count=0 ELSE
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           D   after 1 ns WHEN count=1 ELSE
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           Z0  after 1 ns WHEN count=2 ELSE
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           Z1  after 1 ns WHEN count=3 ELSE
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           ZDX after 1 ns WHEN count=4 ELSE
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           DZX after 1 ns WHEN count=5 ELSE
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           ZX  after 1 ns ;
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  TESTING: PROCESS(count)
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  BEGIN
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    if   count = 0 then
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      ECLK2 <= U   after 1 ns;
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    elsif   count = 1 then
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      ECLK2 <= D   after 1 ns;
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    elsif   count = 2 then
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      ECLK2 <= Z0  after 1 ns;
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    elsif   count = 3 then
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      ECLK2 <= Z1  after 1 ns;
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    elsif   count = 4 then
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      ECLK2 <= ZDX after 1 ns;
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    elsif   count = 5 then
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      ECLK2 <= DZX after 1 ns;
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    else
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      ECLK2 <= ZX  after 1 ns;
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    end if;   
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  END PROCESS TESTING;
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  PROCESS(ECLK,ECLK2)
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  BEGIN
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    if       now =  0 ns then
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      NULL;
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    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 21 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
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      assert FALSE
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        report "FAILED TEST"
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        severity ERROR;
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      ECL <= 0;
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    end if;
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  END PROCESS;
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  PROCESS(ECLK,ECLK2)
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  BEGIN
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    if      (now > 60 ns) and (ECL = 1) then
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      assert FALSE
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        report "***PASSED TEST: c09s05b01x00p01n01i01756"
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        severity NOTE;
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    elsif   (now > 60 ns) and (ECL = 0) then
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      assert FALSE
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        report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
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        severity ERROR;
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    end if;
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  END PROCESS;
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END c09s05b01x00p01n01i01756arch;