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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1717.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1717.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s02b00x00p13n01i01717ent IS
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END c09s02b00x00p13n01i01717ent;
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ARCHITECTURE c09s02b00x00p13n01i01717arch OF c09s02b00x00p13n01i01717ent IS
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  -- Local signals.
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  signal A, B : BIT := '0';
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BEGIN
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  TESTING: PROCESS
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    -- Local variables.
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    variable STARTED: BOOLEAN    := FALSE;
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    variable OldTime: TIME    := 250 ns;
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    variable OldInt : INTEGER    := 13;
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    variable OldA,
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      OldB   : BIT;
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    variable I      : INTEGER;
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  BEGIN
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    -- Initialize variables for this first pass.
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    if  (NOT(STARTED)) then
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      OldTime := NOW;
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      OldInt  := 47;
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      OldA    := A;
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      OldB    := B;
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      I       := 0;
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      STARTED := TRUE;
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    elsif (I > 15) then
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      assert NOT(I = 16) 
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        report "***PASSED TEST: c09s02b00x00p13n01i01717"
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        severity NOTE;
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      assert (I = 16) 
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        report "***FAILED TEST: c09s02b00x00p13n01i01717 - The execution of a process statement consists of the repetitive execution of its sequence of statements."
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        severity ERROR;
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      wait;
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    end if;
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    -- Verify that no variables, time or signals have changed.
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    assert( OldInt = 47 )   severity ERROR;
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    assert( OldTime = NOW ) severity ERROR;
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    assert( OldA = A )      severity ERROR;
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    assert( OldB = B )      severity ERROR;
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    I := I + 1;
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  END PROCESS TESTING;
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  -- This process merely makes assignments to the signals A and B.
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  ASSIGN_PROCESS:   process
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  begin
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    A <= '1' ;
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    B <= '1';
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    wait;
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  end process;
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END c09s02b00x00p13n01i01717arch;