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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1446.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1446.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c08s07b00x00p02n01i01446ent IS
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END c08s07b00x00p02n01i01446ent;
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ARCHITECTURE c08s07b00x00p02n01i01446arch OF c08s07b00x00p02n01i01446ent IS
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  signal     k : integer := 0;
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begin
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  transmit: process
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    variable m : integer := 6;
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  begin
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    if m > 5 then
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      k <= 5;
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    end if;
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    wait for 1 ns;
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    assert (k = 5)
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      report "***FAILED TEST: c08s07b00x00p02n01i01446 - Signal Assignment statement to be sequence statements of IF statement" 
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      severity ERROR;
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    assert NOT(k = 5)
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      report "***PASSED TEST: c08s07b00x00p02n01i01446"
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      severity NOTE;
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    wait;
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  end process;
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END c08s07b00x00p02n01i01446arch;