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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc137.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc137.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c04s03b02x02p08n01i00137ent IS
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END c04s03b02x02p08n01i00137ent;
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ARCHITECTURE c04s03b02x02p08n01i00137arch OF c04s03b02x02p08n01i00137ent IS
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  type    AT0 is array (INTEGER range <>) of INTEGER;
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  subtype ST0 is AT0(1 to 2);
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  type    AT1 is array (INTEGER range <>) of ST0;
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  subtype ST1 is AT1(1 to 2);
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BEGIN
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  TESTING: PROCESS
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    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is      
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    begin
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      if (P = ref) then
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        P := set;
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      end if;
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    end;
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    variable V    : ST1 := ((1, 2), (3, 4));
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    variable V1    : ST0;
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    variable V2    : ST0;
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  BEGIN
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    V1 := (1, 2);
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    V2 := (3, 4);
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    Proc1(  P(1) => V2, P(2) => V1,
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            ref => ((3, 4), (1, 2)), set => ((9, 8), (7, 6))); -- test here
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    assert V1 = (7, 6) report "FAIL: actual V1 didn't get set right";
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    assert V2 = (9, 8) report "FAIL: actual V2 didn't get set right";
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    assert NOT( V1=(7,6) and V2=(9,8) )
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      report "***PASSED TEST: c04s03b02x02p08n01i00137"
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      severity NOTE;
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    assert ( V1=(7,6) and V2=(9,8) )
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      report "***FAILED TEST: c04s03b02x02p08n01i00137 - Association element in an association list test failed."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c04s03b02x02p08n01i00137arch;