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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1350.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1350.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c08s04b01x00p10n01i01350ent IS
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END c08s04b01x00p10n01i01350ent;
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ARCHITECTURE c08s04b01x00p10n01i01350arch OF c08s04b01x00p10n01i01350ent IS
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  signal Add_bus : integer := 67;
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BEGIN
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  TESTING: PROCESS
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  BEGIN
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    Add_bus <= 1 after 5 ns, 6 after 10 ns, 12 after 19 ns;
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    Add_bus <= 6 after 12 ns, 20 after 19 ns, 6 after 21 ns;
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    wait;
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  END PROCESS TESTING;
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  TEST : PROCESS(Add_bus)
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    variable ok : integer := 1;
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  BEGIN
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    if (now = 5 ns) then
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      if (Add_bus /= 67) then
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        ok := 0;
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      end if;
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    elsif (now = 10 ns) then
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      if (Add_bus /= 6) then
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        ok := 0;
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      end if;
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    elsif (now = 12 ns) then
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      if (Add_bus /= 6) then
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        ok := 0;
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      end if;
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    elsif (now = 19 ns) then
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      if (Add_bus /= 20) then
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        ok := 0;
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      end if;
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    end if;
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    if (now = 21 ns) then
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      assert NOT( Add_bus = 6 and ok = 1)
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        report "***PASSED TEST: c08s04b01x00p10n01i01350"
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        severity NOTE;
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      assert ( Add_bus = 6 and ok = 1)
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        report "***FAILED TEST: c08s04b01x00p10n01i01350 - Projected output waveform with initial delay test failed."
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        severity ERROR;
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    end if;
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  END PROCESS TEST;
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END c08s04b01x00p10n01i01350arch;