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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc118.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc118.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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Package c04s03b02x00p29n10i00118pkg is
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  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
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  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
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end c04s03b02x00p29n10i00118pkg;
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use work.c04s03b02x00p29n10i00118pkg.all;
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ENTITY c04s03b02x00p29n10i00118ent IS
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  port (
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    p23 : buffer Boolean        := FALSE;
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    p24 : buffer Bit            := '0'  ;
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    p25 : buffer Character      := NUL  ;
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    p26 : buffer SEVERITY_LEVEL := NOTE ;
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    p27 : buffer Integer        := -1   ;
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    p28 : buffer Real           := -1.0 ;
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    p29 : buffer TIME           := 1 ns ;
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    p30 : buffer Natural        := 0    ;
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    p31 : buffer Positive       := 1    ;
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    p32 : buffer Apollo_string  :=  "abcdefgh";
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    p33 : buffer V_register     := B"10010110"
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    );
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END c04s03b02x00p29n10i00118ent;
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ARCHITECTURE c04s03b02x00p29n10i00118arch OF c04s03b02x00p29n10i00118ent IS
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BEGIN
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  TESTING: PROCESS
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  BEGIN
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    p23  <= not p23 AFTER 10 ns;
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    p24  <= not p24 AFTER 10 ns;
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    if (p25 /= character'high) then
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      p25  <= character'succ (p25) AFTER 10 ns;
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    else
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      p25  <= character'low  AFTER 10 ns;
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    end if;
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    if (p26 /= severity_level'high) then
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      p26  <= severity_level'succ(p26) AFTER 10 ns;
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    else
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      p26  <= severity_level'low  AFTER 10 ns;
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    end if;
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    p27  <= integer'succ(p27) AFTER 10 ns; -- unlikely to overflow....
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    p28  <= p28 + 1.0 AFTER 10 ns;
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    p29  <= p29 * 2 AFTER 10 ns;
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    p30  <= p30 + 1 AFTER 10 ns;
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    p31  <= p31 * 2 AFTER 10 ns;
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    p32(2) <= character'succ (p32(2)) AFTER 10 ns;
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    p33(1) <= not p33(1) AFTER 10 ns;
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    WAIT ON p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33;
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    assert NOT(    p23 = TRUE   and
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                   p24 = '1'     and 
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                   p25 = SOH     and 
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                   p26 = WARNING    and 
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                   p27 = 0      and 
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                   p28 = 0.0    and 
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                   p29 = 2 ns    and 
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                   p30 = 1       and 
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                   p31 = 2       and 
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                   p32 = "accdefgh"and
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                   p33 = B"11010110"   )
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      report "***PASSED TEST: c04s03b02x00p29n10i00118"      severity NOTE;
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    assert (    p23 = TRUE   and
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                p24 = '1'     and 
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                p25 = SOH     and 
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                p26 = WARNING    and 
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                p27 = 0      and 
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                p28 = 0.0    and 
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                p29 = 2 ns    and 
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                p30 = 1       and 
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                p31 = 2       and 
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                p32 = "accdefgh"and
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                p33 = B"11010110"   )
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      report "***FAILED TEST: c04s03b02x00p29n10i00118 - The buffer ports on entities should be able to read."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c04s03b02x00p29n10i00118arch;