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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1027.vhd @ 3fd18385

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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1027.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c06s04b00x00p01n01i01027ent IS
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END c06s04b00x00p01n01i01027ent;
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ARCHITECTURE c06s04b00x00p01n01i01027arch OF c06s04b00x00p01n01i01027ent IS
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BEGIN
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  TESTING: PROCESS
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    variable    V1    : BIT_VECTOR(1 to 2);
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    variable    V2    : BIT_VECTOR(3 to 4);
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    variable   pass   : integer := 0;
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  BEGIN
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    v1(1) := '1';
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    v1(2) := '0';
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    v2(3) := '0';
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    v2(4) := '1';
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    assert v1(1) = '1' report "v1(1) initial value is wrong.";
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    assert v1(2) = '0' report "v1(2) initial value is wrong.";
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    assert v2(3) = '0' report "v2(3) initial value is wrong.";
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    assert v2(4) = '1' report "v2(4) initial value is wrong.";
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    if (   V1(1) /= '1' or V1(2) /= '0' or
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           V2(3) /= '0' or V2(4) /= '1'   ) then   
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      pass := 1;
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    end if;
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    v1 := v2;         -- composite variable assignment
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    assert v1(1) = '0' report "v1(1) final value is wrong.";
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    assert v1(2) = '1' report "v1(2) final value is wrong.";
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    assert v2(3) = '0' report "v2(3) final value is wrong.";
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    assert v2(4) = '1' report "v2(4) final value is wrong.";
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    if (   V1(1) /= '0' or V1(2) /= '1' or
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           V2(3) /= '0' or V2(4) /= '1'   ) then   
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      pass := 1;
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    end if;
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    v1 := ('1', '1');      -- composite variable assignment
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    -- aggregate value
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    assert v1(1) = '1' report "v1(1) final value is wrong.";
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    assert v1(2) = '1' report "v1(2) final value is wrong.";
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    assert v2(3) = '0' report "v2(3) final value is wrong.";
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    assert v2(4) = '1' report "v2(4) final value is wrong.";
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    if (   V1(1) /= '1' or V1(2) /= '1' or
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           V2(3) /= '0' or V2(4) /= '1'   ) then   
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      pass := 1;
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    end if;
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    wait for 5 ns;
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    assert NOT(   pass = 0   )
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      report "***PASSED TEST: c06s04b00x00p01n01i01027"
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      severity NOTE;
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    assert (   pass = 0   )
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      report "***FAILED TEST: c06s04b00x00p01n01i01027 - Indexed reference test failed."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c06s04b00x00p01n01i01027arch;