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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_21_fg_21_05.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity SR_flipflop is
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  port ( s_n, r_n : in bit;  q, q_n : inout bit );
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begin
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  postponed process (q, q_n) is
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            begin
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              assert now = 0 fs or q = not q_n
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                report "implementation error: q /= not q_n";
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            end postponed process;
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                          end entity SR_flipflop;
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--------------------------------------------------
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                                 architecture dataflow of SR_flipflop is
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                                 begin
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                                   gate_1 : q <= s_n nand q_n;
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                                   gate_2 : q_n <= r_n nand q;
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                                 end architecture dataflow;
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-- not in book
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                                 entity fg_21_05 is
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                                 end entity fg_21_05;
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                                 architecture test of fg_21_05 is
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                                   signal s_n, r_n, q, q_n : bit;
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                                 begin
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                                   dut : entity work.SR_flipflop
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                                     port map ( s_n, r_n, q, q_n );
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                                   s_n <= '1',
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                                          '0' after 10 ns, '1' after 15 ns,
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                                          '0' after 30 ns, '1' after 40 ns;
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                                   r_n <= '0', '1' after 5 ns,
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                                          '0' after 20 ns, '1' after 25 ns,
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                                          '0' after 30 ns, '1' after 35 ns;
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                                 end architecture test;
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-- end not in book