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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_21_fg_21_04.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "processor"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "rtl"], "entity" : ["IDENTIFIER", "processor"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "latch"], "generics" : [{
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              "names" : [["IDENTIFIER", "width"]], "typ" : {
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                "name" : ["SIMPLE_NAME", "positive"]}
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              }
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            ], "ports" : [{
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              "names" : [["IDENTIFIER", "d"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                  "ranges" : [["RANGE_WITH_DIRECTION", {
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                    "direction" : "to", "from" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "0"]}
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                        ]]}
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                      ]]}
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                    ], "_to" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "id" : "-", "args" : [["EXPRESSION", {
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                          "args" : [["CALL", ["SIMPLE_NAME", "width"]]]}
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                        ], ["EXPRESSION", {
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                          "args" : [["CONSTANT_VALUE", {
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                            "value" : ["CST_LITERAL", "1"]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]}
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                  ]]}
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                ]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "q"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                  "ranges" : [["RANGE_WITH_DIRECTION", {
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                    "direction" : "to", "from" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "0"]}
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                        ]]}
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                      ]]}
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                    ], "_to" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "id" : "-", "args" : [["EXPRESSION", {
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                          "args" : [["CALL", ["SIMPLE_NAME", "width"]]]}
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                        ], ["EXPRESSION", {
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                          "args" : [["CONSTANT_VALUE", {
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                            "value" : ["CST_LITERAL", "1"]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]}
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                  ]]}
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                ]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "other_port"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_ulogic"]}
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              , "expr" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'-'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "ROM"], "ports" : [{
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              "names" : [["IDENTIFIER", "d_out"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_ulogic_vector"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "other_port"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_ulogic"]}
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              , "expr" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'-'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        , {
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          "definition" : ["SUBTYPE_DECLARATION", {
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            "name" : ["IDENTIFIER", "std_logic_word"], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "to", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "31"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "source1"], ["IDENTIFIER", "source2"], ["IDENTIFIER", "destination"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic_word"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "temp_register"], "inst_unit" : ["SIMPLE_NAME", "latch"], "inst_unit_type" : "component", "generic_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "width"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "32"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["INDEXED_NAME", {
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              "id" : ["SIMPLE_NAME", "std_ulogic_vector"], "exprs" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "destination"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["INDEXED_NAME", {
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              "id" : ["SIMPLE_NAME", "std_logic_vector"], "exprs" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "q"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ], "actual_designator" : ["SIMPLE_NAME", "source1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "constant_ROM"], "inst_unit" : ["SIMPLE_NAME", "ROM"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["INDEXED_NAME", {
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              "id" : ["SIMPLE_NAME", "std_logic_word"], "exprs" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "d_out"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ], "actual_designator" : ["SIMPLE_NAME", "source2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }