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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_12_fg_12_01.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "control_unit"], "generics" : [{
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          "names" : [["IDENTIFIER", "Tpd_clk_out"], ["IDENTIFIER", "Tpw_clk"]], "typ" : {
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            "name" : ["SIMPLE_NAME", "delay_length"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "debug"]], "typ" : {
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            "name" : ["SIMPLE_NAME", "boolean"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CALL", ["SIMPLE_NAME", "false"]]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        ], "ports" : [{
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          "names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ready"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "control1"], ["IDENTIFIER", "control2"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "test"], "entity" : ["IDENTIFIER", "control_unit"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "fg_12_01"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "test"], "entity" : ["IDENTIFIER", "fg_12_01"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "clk"], ["IDENTIFIER", "ready"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "dut1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "control_unit"]]], "inst_unit_type" : "entity", "generic_map" : [{
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            "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "200"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "1500"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "false"]}
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          ], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "ready"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "dut2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "control_unit"]]], "inst_unit_type" : "entity", "generic_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "Tpd_clk_out"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "200"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "Tpw_clk"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "1500"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "ready"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "dut3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "control_unit"]]], "inst_unit_type" : "entity", "generic_map" : [{
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            "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "200"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "1500"], "unit_name" : ["SIMPLE_NAME", "ps"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "debug"], "actual_designator" : ["OPEN"]}
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          ], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "ready"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          , {
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            "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }