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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_11_fg_11_09.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "bus_module"], "ports" : [{
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          "names" : [["IDENTIFIER", "synch"]], "mode" : ["inout"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "other_port"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'U'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "bus_based_system"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "top_level"], "entity" : ["IDENTIFIER", "bus_based_system"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "synch_control"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "label" : ["IDENTIFIER", "synch_control_pull_up"], "lhs" : ["SIMPLE_NAME", "synch_control"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'H'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bus_module_1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "bus_module"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "synch"], "actual_designator" : ["SIMPLE_NAME", "synch_control"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bus_module_2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "bus_module"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "synch"], "actual_designator" : ["SIMPLE_NAME", "synch_control"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }