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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_11_fg_11_04.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity misc_logic is
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end entity misc_logic;
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-- end not in book
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use work.MVL4.all;
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architecture gate_level of misc_logic is
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  signal src1, src1_enable : MVL4_ulogic;
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  signal src2, src2_enable : MVL4_ulogic;
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  signal selected_val : MVL4_logic;
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  -- . . .
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begin
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  src1_buffer : entity work.tri_state_buffer(behavioral)
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    port map ( a => src1, enable => src1_enable, y => selected_val );
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  src2_buffer : entity work.tri_state_buffer(behavioral)
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    port map ( a => src2, enable => src2_enable, y => selected_val );
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  -- . . .
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  -- not in book
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  stimulus : process is
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  begin
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    wait for 10 ns;
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    src1_enable <= '0';  src2_enable <= '0';  wait for 10 ns;
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    src1 <= '0';         src2 <= '1';         wait for 10 ns;
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    src1_enable <= '1';                       wait for 10 ns;
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    src1 <= 'Z';                              wait for 10 ns;
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    src1 <= '1';                              wait for 10 ns;
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    src1_enable <= '0';                       wait for 10 ns;
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    src2_enable <= '1';  wait for 10 ns;
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    src2 <= 'Z';         wait for 10 ns;
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    src2 <= '0';         wait for 10 ns;
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    src2_enable <= '0';  wait for 10 ns;
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    src1_enable <= '1';  src2_enable <= '1';  wait for 10 ns;
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    src1 <= '0';                              wait for 10 ns;
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    src1 <= 'X';                              wait for 10 ns;
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    src1 <= '1';         src2 <= '1';         wait for 10 ns;
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    wait;
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  end process stimulus;
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  -- end not in book
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end architecture gate_level;