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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_07_fg_07_04.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_04 is
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end entity fg_07_04;
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architecture test of fg_07_04 is
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  signal phase1, phase2, reg_file_write_en,
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    A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
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begin
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  -- code from book
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  control_sequencer : process is
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                                procedure control_write_back is
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  begin
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    wait until phase1 = '1';
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    reg_file_write_en <= '1';
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    wait until phase2 = '0';
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    reg_file_write_en <= '0';
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  end procedure control_write_back;
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  procedure control_arith_op is
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  begin
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    wait until phase1 = '1';
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    A_reg_out_en <= '1';
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    B_reg_out_en <= '1';
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    wait until phase1 = '0';
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    A_reg_out_en <= '0';
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    B_reg_out_en <= '0';
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    wait until phase2 = '1';
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    C_reg_load_en <= '1';
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    wait until phase2 = '0';
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    C_reg_load_en <= '0';
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    control_write_back;        -- call procedure
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  end procedure control_arith_op;
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  -- . . .
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  begin
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    -- . . .
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    control_arith_op;          -- call procedure
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    -- . . .
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    -- not in book
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    wait;
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    -- end not in book
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  end process control_sequencer;
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  -- end code from book
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  clock_gen : process is
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  begin
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    phase1 <= '1' after 10 ns, '0' after 20 ns;
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    phase2 <= '1' after 30 ns, '0' after 40 ns;
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    wait for 40 ns;
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  end process clock_gen;
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end architecture test;