Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_07_fg_07_02.vhd @ 3fd18385

History | View | Annotate | Download (2.08 KB)

1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- not in book
28

    
29
entity control_processor is
30
  generic ( Tpd : delay_length := 3 ns );
31
end entity control_processor;
32

    
33
-- end not in book
34

    
35

    
36

    
37
architecture rtl of control_processor is
38

    
39
  type func_code is (add, subtract);
40

    
41
  signal op1, op2, dest : integer;
42
  signal Z_flag : boolean;
43
  signal func : func_code;
44
  -- . . .
45

    
46
begin
47

    
48
  alu : process is
49

    
50
                  procedure do_arith_op is
51
    variable result : integer;
52
  begin
53
    case func is
54
      when add =>
55
        result := op1 + op2;
56
      when subtract =>
57
        result := op1 - op2;
58
    end case;
59
    dest  <=  result after Tpd;
60
    Z_flag  <=  result = 0 after Tpd;
61
  end procedure do_arith_op;
62

    
63
  begin
64
    -- . . .
65
    do_arith_op;
66
    -- . . .
67
    -- not in book
68
    wait on op1, op2, func;
69
    -- end not in book
70
  end process alu;
71

    
72
  -- . . .
73

    
74
  -- not in book
75

    
76
  stimulus : process is
77
  begin
78
    op1 <= 0;  op2 <= 0;	wait for 10 ns;
79
    op1 <= 10; op2 <= 3;	wait for 10 ns;
80
    func <= subtract;		wait for 10 ns;
81
    op2 <= 10;			wait for 10 ns;
82

    
83
    wait;
84
  end process stimulus;
85

    
86
  -- end not in book
87

    
88
end architecture rtl;