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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_07_ch_07_03.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_07_03 is
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end entity ch_07_03;
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library bv_utilities;
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use bv_utilities.bv_arithmetic.all;
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architecture test of ch_07_03 is
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  constant T_delay_adder : delay_length := 10 ns;
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  -- code from book:
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  function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
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  begin
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    -- . . .
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    -- not in book
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    return bv1 + bv2;
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    -- end not in book
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  end function bv_add;
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  signal source1, source2, sum : bit_vector(0 to 31);
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  -- end of code from book
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begin
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  -- code from book:
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  adder : sum <= bv_add(source1, source2) after T_delay_adder;
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  -- end of code from book
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  stimulus : process is
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  begin
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    wait for 50 ns;
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    source1 <= X"00000002";  source2 <= X"00000003";  wait for 50 ns;
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    source2 <= X"FFFFFFF0";  wait for 50 ns;
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    source1 <= X"00000010";                           wait for 50 ns;
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    wait;
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  end process stimulus;
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end architecture test;