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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_06_reg-b.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "reg"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "behavior"], "active_sigs" : [["SIMPLE_NAME", "clk"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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            "if_cases" : [{
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              "if_cond" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["INDEXED_NAME", {
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                        "id" : ["SIMPLE_NAME", "rising_edge"], "exprs" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["EXPRESSION", {
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                                "args" : [["CALL", ["SIMPLE_NAME", "clk"]]]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "q"], "rhs" : [{
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                  "value" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["CALL", ["SIMPLE_NAME", "d"]]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]}
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              ]]}
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            ]}
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          ]]}
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        ]]}
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      ]}
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    ]}
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  }