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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_06_mact-bv.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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architecture bench_verify of mac_test is
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  signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
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  signal x_real, x_imag,
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    y_real, y_imag,
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    behavioral_s_real, behavioral_s_imag,
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    rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
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  type complex is record
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                    re, im : real;
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                  end record;
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  signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
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  constant Tpw_clk : time := 50 ns;
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begin
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  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
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  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
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  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
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  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
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  dut_behavioral : entity work.mac(behavioral)
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    port map ( clk, clr,
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               x_real, x_imag, y_real, y_imag,
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               behavioral_s_real, behavioral_s_imag, behavioral_ovf );
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  dut_rtl : entity work.mac(rtl)
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    port map ( clk, clr,
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               x_real, x_imag, y_real, y_imag,
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               rtl_s_real, rtl_s_imag, rtl_ovf );
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  behavioral_s_real_converter :
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    entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
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  behavioral_s_imag_converter :
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    entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
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  rtl_s_real_converter :
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    entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
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  rtl_s_imag_converter :
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    entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
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  clock_gen : process is
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  begin
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    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
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    wait for 2 * Tpw_clk;
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  end process clock_gen;
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  stimulus : process is
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  begin
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    -- first sequence
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    clr <= '1';  wait until clk = '0';
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    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
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    x <= (+0.2, +0.2);	y <= (+0.2, +0.2);  clr <= '1';	 wait until clk = '0';
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    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '1';	 wait until clk = '0';
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    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
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    -- should be (0.4, 0.58) when it falls out the other end
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    clr <= '0';	 wait until clk = '0';
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    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '0';	 wait until clk = '0';
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    x <= (+0.5, +0.5);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
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    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
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    x <= (-0.5, +0.5);	y <= (-0.5, +0.5);  clr <= '0';	 wait until clk = '0';
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    clr <= '0';	 wait until clk = '0';
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    clr <= '0';	 wait until clk = '0';
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    clr <= '0';	 wait until clk = '0';
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    clr <= '1';	 wait until clk = '0';
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    wait;
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  end process stimulus;
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  verifier : process
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    constant epsilon : real := 4.0E-5;  -- 1-bit error in 15-bit mantissa
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  begin
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    wait until clk = '0';
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    assert behavioral_ovf = rtl_ovf
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      report "Overflow flags differ" severity error;
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    if behavioral_ovf = '0' and rtl_ovf = '0' then
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      assert abs (behavioral_s.re - rtl_s.re) < epsilon
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        report "Real sums differ" severity error;
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      assert abs (behavioral_s.im - rtl_s.im) < epsilon
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        report "Imag sums differ" severity error;
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    end if;
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  end process verifier;
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end architecture bench_verify;