Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_06_mact-bb.vhd @ 3fd18385

History | View | Annotate | Download (3.18 KB)

1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
23
-- $Revision: 1.3 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
library ieee;
28
use ieee.std_logic_1164.all;
29

    
30
architecture bench_behavioral of mac_test is
31

    
32
  signal clk, clr, ovf : std_ulogic := '0';
33
  signal x_real, x_imag,
34
    y_real, y_imag,
35
    s_real, s_imag : std_ulogic_vector(15 downto 0);
36

    
37
  type complex is record
38
                    re, im : real;
39
                  end record;
40

    
41
  signal x, y, s : complex := (0.0, 0.0);
42

    
43
  constant Tpw_clk : time := 50 ns;
44

    
45
begin
46

    
47
  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
48
  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
49
  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
50
  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
51

    
52
  dut : entity work.mac(behavioral)
53
    port map ( clk, clr,
54
               x_real, x_imag, y_real, y_imag, s_real, s_imag,
55
               ovf );
56

    
57
  s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
58
  s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
59

    
60

    
61
  clock_gen : process is
62
  begin
63
    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
64
    wait for 2 * Tpw_clk;
65
  end process clock_gen;
66

    
67

    
68
  stimulus : process is
69
  begin
70
    -- first sequence
71
    clr <= '1';  wait until clk = '0';
72
    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
73
    x <= (+0.2, +0.2);  y <= (+0.2, +0.2);  clr <= '1';  wait until clk = '0';
74
    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '1';  wait until clk = '0';
75
    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
76

    
77
    -- should be (0.4, 0.58) when it falls out the other end
78

    
79
    clr <= '0';  wait until clk = '0';
80
    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '0';  wait until clk = '0';
81
    x <= (+0.5, +0.5);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
82
    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
83
    x <= (-0.5, +0.5);  y <= (-0.5, +0.5);  clr <= '0';  wait until clk = '0';
84
    clr <= '0';  wait until clk = '0';
85
    clr <= '0';  wait until clk = '0';
86
    clr <= '0';  wait until clk = '0';
87
    clr <= '1';  wait until clk = '0';
88

    
89
    wait;
90
  end process stimulus;
91

    
92
end architecture bench_behavioral;