Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_tb_05_08.vhd @ 3fd18385

History | View | Annotate | Download (1.74 KB)

1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_05_tb_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
23
-- $Revision: 1.1.1.1 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
architecture do_nothing of ROM is
28
begin
29
end architecture do_nothing;
30

    
31

    
32
entity tb_05_08 is
33
end entity tb_05_08;
34

    
35

    
36
architecture test of tb_05_08 is
37

    
38
  signal address : natural := 0;
39
  signal data : bit_vector(0 to 7);
40
  signal enable : bit := '0';
41

    
42
begin
43

    
44
  dut : entity work.ROM(do_nothing)
45
    port map ( address => address, data => data, enable => enable );
46

    
47
  stimulus : process is
48
  begin
49
    wait for 100 ns;
50
    address <= 1000;  wait for 10 ns;
51
    enable <= '1', '0' after 10 ns;  wait for 90 ns;
52
    address <= 1004;  wait for 10 ns;
53
    enable <= '1', '0' after 10 ns;  wait for 90 ns;
54
    address <= 1008;  wait for 10 ns;
55
    enable <= '1', '0' after 10 ns;  wait for 90 ns;
56

    
57
    wait;
58
  end process stimulus;
59

    
60
end architecture test;