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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_tb_05_05.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity tb_05_05 is
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end entity tb_05_05;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of tb_05_05 is
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  signal a, b : std_ulogic := '0';
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  signal y : std_ulogic;
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begin
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  dut : entity work.and2(detailed_delay)
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    port map ( a => a, b => b, y => y );
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  stimulus : process is
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  begin
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    wait for 10 ns;
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    a <= '1';	wait for 10 ns;
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    b <= '1';	wait for 10 ns;
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    b <= '0';	wait for 10 ns;
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    b <= '1', '0' after  250 ps;   wait for 10 ns;
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    b <= '1', '0' after  350 ps;   wait for 10 ns;
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    b <= '1', '0' after  450 ps;   wait for 10 ns;
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    b <= '1', '0' after  550 ps;   wait for 10 ns;
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    b <= '1', '0' after  650 ps;   wait for 10 ns;
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    b <= '1', '0' after  750 ps;   wait for 10 ns;
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    b <= '1', '0' after  850 ps;   wait for 10 ns;
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    b <= '1';	wait for 10 ns;
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    b <= '0', '1' after  250 ps;   wait for 10 ns;
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    b <= '0', '1' after  350 ps;   wait for 10 ns;
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    b <= '0', '1' after  450 ps;   wait for 10 ns;
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    b <= 'X';  wait for 10 ns;
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    b <= '0';  wait for 10 ns;
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    b <= 'X', '0' after 250 ps;   wait for 10 ns;
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    wait;
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  end process stimulus;
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end architecture test;