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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_ch_05_22.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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entity mux4 is
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  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
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         z : out bit );
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end entity mux4;
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-- end of code from book
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----------------------------------------------------------------
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architecture functional of mux4 is
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begin
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  out_select : process (sel0, sel1, i0, i1, i2, i3) is
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                                                      subtype bits_2 is bit_vector(1 downto 0);
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  begin
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    case bits_2'(sel1, sel0) is
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      when "00" =>  z <= i0;
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      when "01" =>  z <= i1;
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      when "10" =>  z <= i2;
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      when "11" =>  z <= i3;
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    end case;
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  end process out_select;
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end architecture functional;
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----------------------------------------------------------------
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entity ch_05_22 is
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end entity ch_05_22;
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----------------------------------------------------------------
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architecture test of ch_05_22 is
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  signal select_line, line0, line1, result_line : bit;
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begin
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  -- code from book:
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  a_mux : entity work.mux4
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    port map ( sel0 => select_line, i0 => line0, i1 => line1,
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               z => result_line,
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               sel1 => '0', i2 => '1', i3 => '1' );
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  -- end of code from book
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  ----------------
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  stimulus : process is
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  begin
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    wait for 5 ns;
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    line0 <= '1';				wait for 5 ns;
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    line1 <= '1';				wait for 5 ns;
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    select_line <= '1';	wait for 5 ns;
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    line1 <= '0';				wait for 5 ns;
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    line0 <= '0';				wait for 5 ns;
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    wait;
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  end process stimulus;
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end architecture test;