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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_ch_05_20.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["PACKAGE_DECLARATION", {
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        "name" : ["IDENTIFIER", "pk_05_20"], "shared_defs" : [["TYPE_DECLARATION", {
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          "name" : ["IDENTIFIER", "FIFO_status"], "definition" : ["RECORD_TYPE_DEFINITION", [{
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            "names" : [["IDENTIFIER", "nearly_full"], ["IDENTIFIER", "nearly_empty"], ["IDENTIFIER", "full"], ["IDENTIFIER", "empty"]], "definition" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]]}
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        ]], "shared_decls" : [], "shared_uses" : []}
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      ]}
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    , {
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "pk_05_20"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "FIFO"], "ports" : [{
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          "names" : [["IDENTIFIER", "status"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "FIFO_status"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "other_ports"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "ch_05_20"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "pk_05_20"]]]]]], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "test"], "entity" : ["IDENTIFIER", "ch_05_20"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "start_flush"], ["IDENTIFIER", "end_flush"], ["IDENTIFIER", "DMA_buffer_full"], ["IDENTIFIER", "DMA_buffer_empty"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "DMA_buffer"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "FIFO"]]], "inst_unit_type" : "entity", "port_map" : [{
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            "formal_name" : ["SELECTED_NAME", [["SIMPLE_NAME", "status"], ["IDENTIFIER", "nearly_full"]]], "actual_designator" : ["SIMPLE_NAME", "start_flush"]}
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          , {
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            "formal_name" : ["SELECTED_NAME", [["SIMPLE_NAME", "status"], ["IDENTIFIER", "nearly_empty"]]], "actual_designator" : ["SIMPLE_NAME", "end_flush"]}
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          , {
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            "formal_name" : ["SELECTED_NAME", [["SIMPLE_NAME", "status"], ["IDENTIFIER", "full"]]], "actual_designator" : ["SIMPLE_NAME", "DMA_buffer_full"]}
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          , {
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            "formal_name" : ["SELECTED_NAME", [["SIMPLE_NAME", "status"], ["IDENTIFIER", "empty"]]], "actual_designator" : ["SIMPLE_NAME", "DMA_buffer_empty"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_ports"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }