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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_ch_05_13.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_13 is
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end entity ch_05_13;
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----------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of ch_05_13 is
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  signal s : std_ulogic;
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begin
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  process_05_3_o : process is
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  begin
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    s <= '1' after 11 ns,
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         'X' after 12 ns,
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         '1' after 14 ns,
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         '0' after 15 ns,
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         '1' after 16 ns,
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         '1' after 17 ns,
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         '1' after 20 ns,
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         '0' after 25 ns;
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    wait for 10 ns;
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    -- code from book:
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    s <= reject 5 ns inertial '1' after 8 ns;
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    -- end of code from book
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    wait;
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  end process process_05_3_o;
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end architecture test;