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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_04_tb_04_03.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity test_bench_04_03 is
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end entity test_bench_04_03;
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library ch4_pkgs;
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use ch4_pkgs.pk_04_02.all;
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architecture test_byte_swap_behavior of test_bench_04_03 is
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  signal input, output : halfword := x"0000";
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begin
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  dut : entity work.byte_swap(behavior)
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    port map ( input => input, output => output );
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  stumulus : process is
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  begin
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    wait for 10 ns;
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    input <= x"ff00";	wait for 10 ns;
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    input <= x"00ff";	wait for 10 ns;
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    input <= x"aa33";	wait for 10 ns;
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    wait;
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  end process stumulus;
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end architecture test_byte_swap_behavior;