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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_03_tb_03_10.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity test_bench_03_10 is
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end entity test_bench_03_10;
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architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
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  signal clock : bit := '0'; 
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  signal d_in, d_out : real := 0.0;
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begin
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  dut : entity work.edge_triggered_register(check_timing)
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    port map ( clock => clock, d_in => d_in, d_out => d_out );
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  stumulus : process is
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  begin
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    wait for 20 ns;
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    d_in <= 1.0;			wait for 10 ns;
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    clock <= '1', '0' after 10 ns;	wait for 20 ns;
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    d_in <= 2.0;			wait for 10 ns;
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    clock <= '1', '0' after 5 ns;	wait for 20 ns;
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    d_in <= 3.0;			wait for 10 ns;
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    clock <= '1', '0' after 4 ns;	wait for 20 ns;
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    wait;
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  end process stumulus;
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end architecture test_edge_triggered_register_check_timing;