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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_03_tb_03_09.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_tb_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity test_bench_03_09 is
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end entity test_bench_03_09;
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architecture test_max3_check_error of test_bench_03_09 is
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  signal a, b, c, z : integer := 0;
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begin
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  dut : entity work.max3(check_error)
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    port map ( a => a, b => b, c => c, z => z );
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  stumulus : process is
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  begin
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    wait for 10 ns;
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    a <= 7;				wait for 10 ns;
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    b <= 10;		wait for 10 ns;
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    c <= 15;	wait for 10 ns;
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    a <= 12;				wait for 10 ns;
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    a <= 20;				wait for 10 ns;
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    wait;
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  end process stumulus;
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end architecture test_max3_check_error;