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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_03_ch_03_05.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_05 is
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end entity ch_03_05;
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architecture test of ch_03_05 is
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  type phase_type is (wash, other_phase);
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  signal phase : phase_type := other_phase;
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  type cycle_type is (delicate_cycle, other_cycle);
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  signal cycle_select : cycle_type := delicate_cycle;
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  type speed_type is (slow, fast);
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  signal agitator_speed : speed_type := slow;
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  signal agitator_on : boolean := false;
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begin
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  process_3_1_e : process (phase, cycle_select) is
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  begin
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    -- code from book:
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    if phase = wash then
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      if cycle_select = delicate_cycle then
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        agitator_speed <= slow;
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      else
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        agitator_speed <= fast;
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      end if;
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      agitator_on <= true;
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    end if;
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    -- end of code from book
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  end process process_3_1_e;
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  stimulus : process is
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  begin
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    cycle_select <= other_cycle;	wait for 100 ns;
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    phase <= wash;			wait for 100 ns;
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    cycle_select <= delicate_cycle;	wait for 100 ns;
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    cycle_select <= other_cycle;	wait for 100 ns;
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    phase <= other_phase;		wait for 100 ns;
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    wait;
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  end process stimulus;
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end architecture test;