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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_01_fg_01_10.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_01_fg_01_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity d_latch is
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  port ( d, clk : in bit;  q : out bit );
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end d_latch;
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entity and2 is
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  port ( a, b : in bit;  y : out bit );
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end and2;
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architecture basic of d_latch is
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begin
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  latch_behavior : process is
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  begin
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    if clk = '1' then
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      q <= d after 2 ns;
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    end if;
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    wait on clk, d;
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  end process latch_behavior;
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end architecture basic;
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architecture basic of and2 is
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begin
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  and2_behavior : process is
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  begin
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    y <= a and b after 2 ns;
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    wait on a, b;
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  end process and2_behavior;
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end architecture basic;