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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ap_a_fg_a_09.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity fg_a_09 is
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end entity fg_a_09;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of fg_a_09 is
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  signal clk25M, resetl : std_ulogic;
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  signal data, odat : std_ulogic_vector(7 downto 0);
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begin
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  -- code from book
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  wrong_way : process ( clk25M, resetl, data )
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  begin
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    if resetl = '0' then
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      odat <= B"0000_0000";
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    elsif rising_edge(clk25M) then
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      odat <= data;
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    elsif data = B"0000_0000" then
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      odat <= B"0000_0001";
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    end if;
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  end process wrong_way;
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  -- end code from book
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  data <= odat(6 downto 0) & '0';
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  clk_gen : process is
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  begin
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    clk25M <= '0', '1' after 10 ns;
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    wait for 20 ns;
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  end process clk_gen;
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  resetl <= '1', '0' after 20 ns, '1' after 60 ns;
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end architecture test;