Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ap_a_fg_a_05.vhd @ 3fd18385

History | View | Annotate | Download (2.27 KB)

1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ap_a_fg_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
23
-- $Revision: 1.1.1.1 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity fg_a_05 is
28

    
29
end entity fg_a_05;
30

    
31

    
32
library ieee;  use ieee.std_logic_1164.all;
33

    
34
architecture test of fg_a_05 is
35

    
36
  signal clk, reset, a, b, x, q : std_ulogic;
37

    
38
begin
39

    
40
  -- code from book
41

    
42
  ff2 : process (reset, clk) is
43
  begin
44
    if reset = '1' then
45
      q <= '0';
46
    elsif rising_edge(clk) then
47
      if x = '1' then
48
        q <= a;
49
      else
50
        q <= b;
51
      end if;
52
    end if;
53
  end process ff2;
54

    
55
  -- end code from book
56

    
57
  stimulus : process is
58
  begin
59
    reset <= '0';  clk <= '0';  x <= '1'; a <= '1'; b <= '0';  wait for 10 ns;
60
    reset <= '1', '0' after 30 ns;
61
    clk <= '1' after 10 ns, '0' after 20 ns;
62
    wait for 40 ns;
63
    clk <= '1', '0' after 2 ns,
64
           '1' after 12 ns, '0' after 14 ns,
65
           '1' after 17 ns, '0' after 19 ns,
66
           '1' after 22 ns, '0' after 24 ns,
67
           '1' after 27 ns, '0' after 29 ns,
68
           '1' after 32 ns, '0' after 34 ns,
69
           '1' after 37 ns, '0' after 39 ns,
70
           '1' after 42 ns, '0' after 44 ns,
71
           '1' after 47 ns, '0' after 49 ns;
72
    a <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
73
    b <= '0' after 15 ns, '1' after 25 ns, '0' after 35 ns, '1' after 45 ns;
74
    x <= '0' after 30 ns;
75

    
76
    wait;
77
  end process stimulus;
78

    
79
end architecture test;
80