Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ap_a_fg_a_04.vhd @ 3fd18385

History | View | Annotate | Download (1.7 KB)

1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
23
-- $Revision: 1.1.1.1 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity fg_a_04 is
28

    
29
end entity fg_a_04;
30

    
31

    
32
library ieee;  use ieee.std_logic_1164.all;
33

    
34
architecture test of fg_a_04 is
35

    
36
  signal clk, reset, d, q, q_n : std_ulogic;
37

    
38
begin
39

    
40
  -- code from book
41

    
42
  ff1 : process (reset, clk) is
43
  begin
44
    if reset = '1' then
45
      q <= '0';
46
    elsif rising_edge(clk) then
47
      q <= d;
48
    end if;
49
  end process ff1;
50

    
51
  q_n <= not q;
52

    
53
  -- end code from book
54

    
55
  stimulus : process is
56
  begin
57
    reset <= '0';  clk <= '0';  d <= '1';  wait for 10 ns;
58
    reset <= '1', '0' after 30 ns;
59
    clk <= '1' after 10 ns, '0' after 20 ns;
60
    wait for 40 ns;
61
    clk <= '1', '0' after 20 ns;
62
    d <= '0' after 10 ns;
63

    
64
    wait;
65
  end process stimulus;
66

    
67
end architecture test;
68