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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ap_a_ap_a_08.vhd @ 3fd18385

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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_ap_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity entname is
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               end entity entname;
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               architecture rtl of entname is
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                 -- code from book
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                 subtype state_type is std_ulogic_vector(3 downto 0);
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                 constant s0 : state_type := "0001";
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                 constant s1 : state_type := "0010";
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                 constant s2 : state_type := "0100";
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                 constant s3 : state_type := "1000";
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                 -- end code from book
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                 signal state, next_state : state_type;
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                 signal con1, con2, con3 : std_ulogic;
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                 signal out1, out2 : std_ulogic;
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                 signal clk, reset : std_ulogic;
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               begin
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                 state_logic : process (state, con1, con2, con3) is
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                 begin
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                   case state is
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                     when s0 =>
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                       out1 <= '0';
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                       out2 <= '0';
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                       next_state <= s1; 
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                     when s1 =>
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                       out1 <= '1';
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                       if con1 = '1' then
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                         next_state <= s2;
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                       else
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                         next_state <= s1;
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                       end if;
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                     when s2 =>
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                       out2 <= '1';
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                       next_state <= s3;
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                     when s3 =>
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                       if con2 = '0' then
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                         next_state <= s3;
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                       elsif con3 = '0' then
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                         out1 <= '0';
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                         next_state <= s2;
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                       else
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                         next_state <= s1;
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                       end if;
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                     when others =>
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                       null;
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                   end case;
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                 end process state_logic;
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                 state_register : process (clk, reset) is
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                 begin
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                   if reset = '0' then
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                     state <= s0;
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                   elsif rising_edge(clk) then
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                     state <= next_state;
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                   end if;
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                 end process state_register;
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                 clk_gen : process is
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                 begin
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                   clk <= '0', '1' after 10 ns;
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                   wait for 20 ns;
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                 end process clk_gen;
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                 reset <= '0', '1' after 40 ns;
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                 con1 <= '0', '1' after 100 ns, '0' after 120 ns;
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                 con2 <= '0', '1' after 160 ns;
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                 con3 <= '0', '1' after 220 ns;
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               end architecture rtl;