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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / ticket92 / cover_report2.vhd @ 3fd18385

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library ieee;
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  use ieee.std_logic_1164.all;
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library std;
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  use std.env.all;
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entity cover_report2 is
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end entity cover_report2;
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architecture test of cover_report2 is
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  signal s_a   : std_logic;
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  signal s_b   : std_logic;
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  signal s_c   : std_logic;
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  signal s_clk : std_logic := '0';
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begin
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  s_clk <= not(s_clk) after 5 ns;
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  process is
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  begin
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    s_a <= '0';
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    s_b <= '0';
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    s_c <= '0';
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    wait until rising_edge(s_clk);
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    s_a <= '1';
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    wait until rising_edge(s_clk);
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    s_a <= '0';
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    s_b <= '1';
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    wait until rising_edge(s_clk);
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    s_b <= '0';
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    s_c <= '1';
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    wait until rising_edge(s_clk);
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    s_c <= '0';
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    stop(0);
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  end process;
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  -- psl default clock is rising_edge(s_clk);
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  --
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  -- psl sequence test_p is {s_a; s_b};
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  --
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  -- DOES WORK
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  -- -- psl TEST : cover test_p;
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  --
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  -- DOESN'T WORK:
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  -- psl cover test_p report "Covered";
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end architecture test;